Please use this identifier to cite or link to this item:
|Title:||From Statecharts to Verilog: A formal approach to hardware/software co-specification|
|Source:||Qin, S.,Chin, W.-N.,He, J.,Qiu, Z. (2006). From Statecharts to Verilog: A formal approach to hardware/software co-specification. Innovations in Systems and Software Engineering 2 (1) : 17-38. ScholarBank@NUS Repository. https://doi.org/10.1007/s11334-005-0020-2|
|Abstract:||Hardware/software co-specification is a critical phase in co-design. Our co-specification process starts with a high level graphical description in Statecharts and ends with an equivalent parallel composition of hardware and software descriptions in Verilog. In this paper, we first investigate the Statecharts formalism by providing it a formal syntax and a compositional operational semantics. Based on that, a semantics-preserving linking function is designed to compile specifications written in Statecharts into Verilog. The obtained Verilog specifications are then passed to a partitioning process to generate hardware and software subspecifications, where the correctness is guaranteed by algebraic laws of Verilog. © Springer-Verlag Berlin Heidelberg 2006.|
|Source Title:||Innovations in Systems and Software Engineering|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Jan 16, 2018
checked on Jan 21, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.