Advanced Silicon and Germanium Transistors for Future P-channel MOSFET Applications

Abstract

Continual scaling of Si CMOS into deep sub-20 nm regime meets some immense challenges. The motivation of this thesis is to provide feasible solutions to some of the technical challenges. The smaller space available in between the gate electrodes due to aggressive pitch scaling compromises strain in the channel. To address this challenge, new diamond-like carbon (DLC) liner stressor with direct integration onto Si p-FETs, including planar and nanowire p-FETs, was developed for performance enhancement. Negative Bias Temperature Instability study was performed on p-FETs with different levels of channel strain, investigating the strain effect on NBTI characteristics. In addition, we developed high performance Ge multiple-gate FETs (MuGFETs) based on Ge on insulator substrates to have high performance transistors with good short channel control. Implantless metallic Schottky barrier (SB) source/drain (S/D) and in-situ doped raised S/D (RSD) structures were reported for the first time for Ge MuGFETs.