Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/32718
Title: Process flow for a performance enhanced MOSFET with self-aligned, recessed channel
Authors: SNEELAL, SNEEDHARAN PILLAI
POH, FRANCIS
LEE, JAMES
SEE, ALEX 
LAU, C. K. 
SAMUDRA, GANESH SHANKAR 
Issue Date: 15-Aug-2006
Source: SNEELAL, SNEEDHARAN PILLAI,POH, FRANCIS,LEE, JAMES,SEE, ALEX,LAU, C. K.,SAMUDRA, GANESH SHANKAR (2006-08-15). Process flow for a performance enhanced MOSFET with self-aligned, recessed channel. ScholarBank@NUS Repository.
Abstract: A method for forming a self-aligned, recessed channel, MOSFET device that alleviates problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is described. A thin pad oxide layer is grown overlying the substrate and a gate recess, followed by deposition of a thick silicon nitride layer filling the gate recess. The top surface is planarized exposing the pad oxide layer. An additional oxide layer is grown, thickening the pad oxide layer. A portion of the silicon nitride layer is etched away and additional oxide layer is again grown. This forms a tapered oxide layer along the sidewalls of the gate recess. The remaining silicon nitride layer is removed. The oxide layer at the bottom of the gate recess is removed and a gate dielectric layer is grown. Gate polysilicon is deposited filling the gate recess. S/D implantations, metallization, and passivation complete fabrication of the device.
URI: http://scholarbank.nus.edu.sg/handle/10635/32718
Appears in Collections:Staff Publications

Show full item record
Files in This Item:
File Description SizeFormatAccess SettingsVersion 
US7091092.PDF137.46 kBAdobe PDF

OPEN

PublishedView/Download

Page view(s)

161
checked on Dec 15, 2017

Download(s)

81
checked on Dec 15, 2017

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.