Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/32698
Title: Wafer level super stretch solder
Authors: WONG, EE HUA 
RAJOO, RANJAN
TEO, POI SIONG 
Issue Date: 10-May-2005
Source: WONG, EE HUA,RAJOO, RANJAN,TEO, POI SIONG (2005-05-10). Wafer level super stretch solder. ScholarBank@NUS Repository.
Abstract: We disclose a technique to generate stretched solder columns (bumps) at the wafer level, suitable for wafer level packaging. This is accomplished through use of using two wafers—the standard (functional) wafer that contains the integrated circuits and a master (dummy) wafer on whose surface is provided an array of solder bumps that is the mirror image of that on the functional wafer. After suitable alignment, both sets of solder bumps are melted and then slowly brought together till they merge. Then, as they cool, they are slowly pulled apart thereby stretching the merged solder columns. Once the latter have fully solidified, they are separated from the master wafer only.
URI: http://scholarbank.nus.edu.sg/handle/10635/32698
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