Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/32598
Title: Method to reduce compressive stress in the silicon substrate during silicidation
Authors: CHA, RANDALL CHER LIANG
CHUA, CHEE TEE
PEY, KIN LEONG 
CHAN, LAP
Issue Date: 4-Sep-2001
Source: CHA, RANDALL CHER LIANG,CHUA, CHEE TEE,PEY, KIN LEONG,CHAN, LAP (2001-09-04). Method to reduce compressive stress in the silicon substrate during silicidation. ScholarBank@NUS Repository.
Abstract: A method for siliciding source/drain junctions is described wherein compressive stress of the underlying silicon is avoided by the insertion of a buffer layer between the silicide and the silicon. A gate electrode and associated source/drain extensions are provided in and on a semiconductor substrate. A buffer oxide layer is deposited overlying the semiconductor substrate and the gate electrode. A polysilicon layer is deposited overlying the buffer oxide layer. The polysilicon layer will form the source/drain junctions and silicon source. The source/drain junctions are silicided whereby the buffer oxide layer provides compressive stress relief during the siliciding.
URI: http://scholarbank.nus.edu.sg/handle/10635/32598
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