Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/32347
Title: LOW-VOLTAGE LOW-POWER ANALOG-TO-DIGITAL CONVERTERS
Authors: TAO YONGHONG
Keywords: low-voltage, low-power, Delta-Sigma, input feedforward, successive-approximation, current-mode
Issue Date: 25-Nov-2011
Source: TAO YONGHONG (2011-11-25). LOW-VOLTAGE LOW-POWER ANALOG-TO-DIGITAL CONVERTERS. ScholarBank@NUS Repository.
Abstract: Low voltage, low power analog-to-digital converters (ADCs) are critical in many applications. This thesis covers two popular ADC designs: Delta-Sigma modulator and Successive-approximation (SAR) ADC. The Delta-Sigma modulator is targeted for digital subscriber line (DSL) application, which requires an ADC with 13~14 bit resolution. With the supply voltage of 1 V, one modulator is implemented to achieve 2.5 MS/s conversion rate for ADSL, while another modulator is proposed to achieve 25 MS/s conversion rate for VDSL. The input feedforward topology is the key for low power consumption. Two single-ended, 10-bit SAR ADCs for bio-sensing applications are also presented, with supply voltage of 1.0 and 0.8 V respectively. Both ADCs achieve the conversion rate of 1 MS/s, which enables time multiplexing between multiple channels. The current-mode comparator and reused single-stage amplifier are key concepts for low power consumption. The achieved Figure-of-Merit (FoM) is 35 and 20 fJ/conversion respectively.
URI: http://scholarbank.nus.edu.sg/handle/10635/32347
Appears in Collections:Ph.D Theses (Open)

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