Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/31648
Title: 50-250MHZ ?S DLL for Clock Synchronization
Authors: CHENG SAN JEOW
Keywords: delta-sigma, DLL, clock synchronization, CMOS, jitter, resolution
Issue Date: 14-Apr-2011
Source: CHENG SAN JEOW (2011-04-14). 50-250MHZ ?S DLL for Clock Synchronization. ScholarBank@NUS Repository.
Abstract: With the advent of high data rate wireline applications in microprocessors and memory integrated circuits, clock skew becomes a significant factor of the overall timing margin issue in system design. A delay locked loop (DLL) is often used for flexible timing control not only in source-synchronous serial interfaces but also in clock-and-data recovery systems. A digitally controlled delay line is preferred over its analog counterpart due to its better testability and robust characteristics. Although the semi-digital or all-digital DLL may have more robust delay control, achieving fine timing resolution comparable to that of an analog delay line is still challenging due to minimum achievable delay resolution posed by technology limitations. Spurred by demands of fine tuning resolution, low jitter performance and operation robustness, the aim of this research work is to address these issues in a digitally controlled DLL. A delta-sigma modulator based DLL architecture for clock synchronization application is designed and fabricated in 0.35?m CMOS technology as a proof of concept for demonstrating the fine timing resolution and low jitter performance achievable by such architecture. By incorporating a delta-sigma modulator in the DLL, it can have a fractional step delay of 15ps and can operate from 50 MHz to 250 MHz. It draws about 6.9 mA from 3 V supply at 200 MHz. Unlike other existing delta-sigma DLL designs, the proposed DLL makes use of the delta-sigma modulator in the feedback path rather than at the input, which enables it to eliminate the additional multi-phase generator. Besides the simplification in architecture, it also has 2 novel features, a second order filter whose 2 poles can be adaptively adjusted and a unique anti-harmonic detector. Through simplification in the structure and noise shaping contribution from the delta-sigma modulator, it exhibits a low rms jitter of 2.137 ps. Hence, the proposed digitally controlled DLL is straightforward and combines digital architecture robustness with fine tuning resolution similar to analog designs.
URI: http://scholarbank.nus.edu.sg/handle/10635/31648
Appears in Collections:Ph.D Theses (Open)

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