On the road towards robust and ultra low energy CMOS digital circuits using sub/near threshold power supply

Abstract

This thesis presents designing of robust near/sub-threshold CMOS digital circuits. While previous research uses ultra-low voltage operation only for low-throughput applications, we achieve medium throughput using architectural-level parallelism. Several physical-level techniques are also proposed to mitigate yield loss due to process variations, such as balancing VT of n/pMOS transistors, using VT mismatch between parallel transistors to improve driving capability, selecting and modifying standard cells, etc. These ideas are demonstrated using SubJPEG, a state-of-the-art 65nm CMOS standard VT JPEG co-processor. In the sub-threshold, each DCT and Quantization engine dissipates only 0.75pJ per cycle with a 0.4V supply at 2.5MHz frequency, which leads to 8.3X energy reduction compared to using the 1.2V nominal supply. In the near-threshold, each engine dissipates only 1.0pJ per cycle with a 0.45V supply at 4.5MHz frequency, but the system throughput still meets the VGA standard requirement for 15 fps 640C 480 pixel.