High mobility III-V compound semiconductors for advanced transistor applications

Abstract

The continual geometrical scaling of Si MOSFET into nanoscale regime for improved device performance and density is rapidly approaching its fundamental limitations. Fundamental changes to the materials and device structures are deemed to hold great promises for the evolution of future CMOS technologies. High mobility III-V compound semiconductors have received renewed interest as alternative materials to replace conventional Si or strained Si channels and to be heterogeneously integrated on Si or silicon-on-insulator (SOI) substrates for advanced CMOS technology beyond the 22 nm technology node. To take full advantage of the III-V, a gate dielectric process technology that provides good interfacial properties is required. In this thesis, effective and highly manufacturable passivation technology based on a multiple chamber MOCVD system was demonstrated. The key characteristics of these new in-situ passivation technologies using silane (SiH4), silane and ammonia (SiH4+NH3), and post-gate dielectric deposition treatment in tetrafluoromethane (CF4) plasma were determined and identified. Technology demonstrations in various III-V MOSFETs exhibit good transistor characteristics. This affirms the effectiveness of the designed concept for interface engineering for native oxide reduction. Further enhancement of III-V MOSFETs by the integration of in-situ doped lattice-mismatched S/D stressors for source/drain (S/D) doping and channel strain engineering is also investigated. This work explores novel In0.53Ga0.47As N-channel MOSFET with in-situ doped In0.4Ga0.6As S/D regions. The high S/D doping concentration, achieved by the in situ doping process, further reduces S/D series resistance (RSD) for additional performance improvement. In addition, the lattice mismatch between In0.4Ga0.6As S/D and In0.53Ga0.47As channel is exploited to induce tensile strain in the channel for mobility enhancement. For achieving better electrostatic control than planar FETs, novel InGaAs multiple-gate FET (MuGFET) or FinFET for enhanced carrier mobility, and an epi-controlled retrograde-doped fin to suppress short channel effects is explored. Transistor output characteristics with high saturation drain current and transconductance were obtained. In addition, significant improvement in the short channel effects, such as drain-induced barrier lowering (DIBL), as compared to planar MOSFETs was achieved. In addition, a new method of forming GaAs on a Si-based substrate through selective migration-enhanced epitaxy (MEE) of GaAs on strain-compliant SiGe nanowire structures was reported. Good material property and growth selectivity were realized. This new III-V integration scheme may be promising for integrating high speed transistors and optoelectronic devices with advanced electronic circuits on Si platform.