B*tree representation based thermal and variability aware floorplanning frame work

Abstract

The evolution of deep submicron technologies has placed a high importance on power dissipation and temperature of the chip. In addition, the increasing design complexity is causing higher levels of uncertainty in design prototyping in the early chip planning stages thus leading to parameter variations which are posing an ever-increasing challenge to performance analysis of high-speed designs. The purpose of the thesis is to develop a B*-Tree based floorplanner with two major objectivesFirst, we present an interconnect and thermal-aware floorplanner that aims at reducing hot spots and distributing temperature evenly across a chip while optimizing the traditional design metrics, chip area and wirelength. It considers the switching activity of interconnects in deriving interconnect power dissipation and in exploring a thermal-aware floorplan which most prior work have failed to do. This can result in peak temperatures being underestimated by as much as 15oC according to our experiments. Results demonstrate that our floorplanner is effective in lowering peak temperatures by 20% on the average while providing area compacted floorplans with just a slight overhead of total wirelength by 2% when testing with MCNC benchmarks.Second, we use an affine arithmetic (AA) model to develop a fast and optimized variability-aware floorplanner to enable an accurate estimation of the variable range of floorplan metrics such as area and wirelength in the presence of variations of each blocka??s dimensions. Compared with the Monte Carlo simulation results, the average errors of mean and range values computed by the proposed method are a??0.78% & a??12.96% respectively for area, a??2.43% & a??13.23% respectively for wirelength and up to 100X speed up by testing on five MCNC benchmarks.