Low-voltage low-power continuous-time delta-sigma modulator designs

Abstract

Driven by the growing market of portable products, low-power design issue becomes more and more important in recent years. The low-power trend for the digital circuitry has been achieved by the scaling CMOS technology, which keeps offering transistors smaller size and lower supply voltage. However, the supply voltage reduction considerably degrades the performance of the analog/mixed-signal circuits, e.g. the analog-to-digital converter. As a promising candidate for the analog-to-digital conversion, the Delta-Sigma modulator has obtained many attentions from the industry and the academic. This research has focused on the low-voltage low-power Delta-Sigma modulator designs in the advanced CMOS technology. Various efforts have been devoted on the system-level and the circuit-level. On the system-level, the continuous-time input-feedforward topology is adopted due to its attractive potential for low-voltage and low-power designs. The design method for the continuous-time topology is presented. Simulink-based models for the continuous-time Delta-Sigma modulator are proposed. Based on the models, nonidealities in the CT Delta-Sigma modulator are simulated and analyzed, and their solutions are given. Three design examples are presented. The first design is a 1.2-V 4th-order single-bit wideband Delta-Sigma modulator. A novel structure is proposed for implementing the feedforward and summing part. Implemented in a 0.13-?m CMOS technology, this design achieves 68-dB dynamic range over 1.25-MHz signal bandwidth with a 160-MHz sampling frequency. The power consumption is 2.7-mW, and the core area of the modulator is 0.082 mm2. The measurement results verify that the proposed feedforward and summing structure is effective to reduce the power consumption with a small silicon area. The second design is a 1-V 4th-order 1.5-bit audio Delta-Sigma modulator. The 1.5-bit input-feedforward topology with optimized coefficients is used. The feedforward and summing part is embedded into the 1.5-bit quantizer. A simple dynamic element matching circuit is designed to improve linearity. Designed in a 0.13-?m CMOS technology, the modulator shows a peak signal-to-quantization noise and distortion ratio of 97.3-dB over 20-kHz signal bandwidth. The power consumption is 42.6-?W, and the chip area is 0.125 mm2. Compared to other low-voltage audio Delta-Sigma modulators, this design shows very low power and very small area. The third design is a 0.6-V 4th-order single-bit audio Delta-Sigma modulator. A simple and power-efficient amplifier structure with body-driven gain-enhanced technique is proposed. A novel rail-to-rail input common-mode feedback circuit is presented for the low-voltage operation. Implemented in a 0.13-?m CMOS technology, the design shows an 82-dB dynamic range with 28.6-?W power consumption. The measurement results show that with the proposed circuits the design achieves low power consumption, while maintaining a good resolution.