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Title: Lanthanoid based materials in advanced CMOS technology
Keywords: Lanthanoid, CMOS, Schottky Barrier MOSFET, High-k, metal gate, MIM capacitor
Issue Date: 28-Oct-2009
Source: CHEN JINGDE (2009-10-28). Lanthanoid based materials in advanced CMOS technology. ScholarBank@NUS Repository.
Abstract: Aggressive complementary metal-oxide-semiconductor (CMOS) scaling requires the development of new materials and device architectures. This dissertation focuses on introducing lanthanoid based materials into CMOS technology to address some of the new challenges in CMOS scaling. The low work function lanthanoid silicides are potential candidates for N-type Schottky source/drain field-effect transistor (N-SSDT). Several lanthanoid elements, including Dy, Er, Tb and Yb, were investigated to form the self-aligned silicide (salicide) S/D for N-SSDT. The YbSi<sub>2-x</sub> has been found to be a very promising candidate for N-SSDT as it provides a high drive current with a very low leakage current. By addressing the compatibility issues of lanthanoid materials with conventional CMOS process, a low temperature, implantation free MOSFET process featuring a ?hole spacer?, Schottky barrier source/drain, high-&kappa; dielectric and metal gate electrode was successfully developed. The elimination of polysilicon gate depletion effect and reduction in gate leakage current are major advantages of metal gate/high-&kappa; dielectric gate stack over conventional polysilicon/SiO(N) gate stack. However, achieving the desired effective metal gate work function &Phi;<sub>m</sub> to meet threshold voltage requirements in future CMOS devices is one of the main hurdles for its implementation. We demonstrate two methods for tuning the metal gate work function towards the silicon conduction band edge. The first one is to incorporate ytterbium (Yb) into Ni fully-silicided (Ni-FUSI) gate. Yb has a low work function of 2.59 eV. During the silicidation process, Yb atoms accumulate at the NiSi/SiO<sub>2</sub> interface and achieved a FUSI gate &Phi;<sub>m</sub> lowering of about 0.3 to 0.5 eV. However, this method is less effective on high-&kappa; dielectrics. The second method is to incorporate lanthanoid oxides into hafnium oxide gate dielectric. Conduction band-edge TaN gate &Phi;<sub>m</sub> values of 4.1 to 4.24 eV were obtained by doping HfO<sub>2</sub> gate dielectric with Er<sub>2</sub>O<sub>3</sub> and several other lanthanoid oxides. Interface dipole models were discussed to explain the effective gate &Phi;<sub>m</sub> tunability. After addressing the challenges active device, we explore the scaling down of metal-insulator-metal (MIM) capacitors by investigating a series of lanthanoid oxides as candidates for the insulator layer. MIM capacitors using Sm<sub>2</sub>O<sub>3</sub> or Er<sub>2</sub>O<sub>3</sub> dielectric material were found to have better voltage linearity as compared with other high-&kappa; materials at the same capacitance density. Satisfactory leakage current and frequency dispersion properties indicate that both oxides are promising. It was found that both oxygen vacancy in the dielectric film and the interfacial layer at the high-&kappa;/bottom electrode interface played an important role in the voltage linearity of the MIM stack. An innovative dielectric structure is developed by intentionally inserting a thin SiO<sub>2</sub> layer between the lanthanoid oxide and bottom electrode. We achieved high capacitance density (up to 8.5 fF/?m<sup>2</sup>) with quadratic VCC lower than 100 ppm/V<sup>2</sup> by engineering the thickness ratio of high-&kappa; to SiO<sub>2</sub> layers. This performance can meet the International Technology Roadmap for Semiconductors (ITRS) requirements in 2013 and indicates that MIM capacitors with high-&kappa;/SiO<sub>2</sub> dielectric stack can be a long-term solution to RF and analog/mixed-signal capacitor technology.
Appears in Collections:Ph.D Theses (Open)

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