Sigma-delta class D audio power amplifier in CMOS technology

Abstract

This thesis presents detail design flow of a single chip class D audio power amplifier which is realized in 0.35um CMOS technology. This design consists of a high-linear single-loop feed-forward Sigma-Delta modulator with three level quantizer and a full H-bridge output stage. The three-level quantizer effectively reduces the switching activity of the output stage, especially when the input signal amplitude is low. Hence the power efficiency is improved. Direct feedback from H-bridge output improves the linearity of the amplifier. This design has been fabricated and sample chips are tested for the performance evaluation. With 3.3-V supply voltage and 4-Ohm load, the amplifier can deliver maximum 1-W output power. The best THD+N is 0.08% at 1kHz. The PSRR measured is 64dB and the maximum power efficiency of this design is 80%.