Fabrication, characterization, and modeling of silicon multi-gate devices

Abstract

As multi-gate devices such as FinFET and nanowire FETs emerges as leading contenders of the future generation electron devices, detailed study of their electrical properties, characterization as well as effective modeling solution are much needed before they become truly viable for industrial application. This dissertation addresses the fabrication, characterization and modeling of silicon multi-gate transistors fabricated using the conventional CMOS platform. Its main purpose is to overcome some major challenges in both device fabrication and sub-femto farad capacitance measurement and modeling. A study of three dimensional electric field provided valuable insights to device operation and optimization for multi-gate devices. Charge Based Capacitance Measurement (CBCM) was simulated, analyzed, verified and applied for the first time to measurement of sub-femto farad voltage dependent capacitances. CBCM test keys were designed and fabricate for measurements of sub-femto scale nanowire capacitance. Also, measurement of charge and capacitance on single channel nanowire devices were used for self-consistent tight-binding computation of intrinsic and extrinsic capacitance calculation and extraction of series resistance and carrier mobility.