Top-down Si nanowire technology in discrete charge storage nonvolatile memory application

Abstract

The commercial flash memory, which currently uses a polysilicon floating gate as the charge storage material, has faced issues of non-scalability of the tunnel oxide and interpoly dielectric in the course of scaling, due to the significantly reduced coupling ratio and serious gate interference. Due to scaling limitations of the conventional floating-gate nonvolatile flash memory cells, another type of nonvolatile memory based on discrete charge trapping is currently being considered as a promising alternative. The discrete charge storage nonvolatile memories are immune to local defect related leakage due to isolated charge storage nodes, providing larger scaling capability than floating gate devices. This thesis proposes methodologies to resolve issues of gate stack scaling and voltage scaling in the SONOS type discrete charge storage nonvolatile memory in order to increase the possibility of it being employed in future semiconductor nonvolatile memory application. This thesis discusses solutions to scale the discrete trapped charge-storage nonvolatile memory based on a state-of-the-art non-traditional structure ¿ a gate-all-around nanowire channel structure ¿ whose fabrication method completely follows the CMOS-compatible rule in order to increase industrial adaptability of this novel technology. A high-speed SONOS nonvolatile memory cell with a gate-all-around (GAA) Si-nanowire architecture is discussed in detail. The method of fabricating vertically stacked top-down nanowires with 5-nm diameter is highlighted. The nanowire SONOS device exhibits evident improvements in low voltage programming and fast programming and erasing speeds with regards to the planar control device. Theperformance enhancement mechanism shall be explained by device modeling which investigates electron energy distribution, potential energy profile and electric field along each layer surrounding the nanowire channel. The gate-all-around nanowire channel structure is introduced into the poly-Si memory as a promising methodology to resolve issues of poor device subthreshold performance, low memory speed and inferior device uniformity in low temperature polycrystalline Si TFT memory devices, which can be integrated in future system-on-panel and system-on-chip applications. A strategy of optimizing SONOS-type memory characteristics is illustrated and discussed by integrating high-¿ dielectric materials and metal gate electrode. The application of high-¿ materials and TaN metal gate electrode, used to replace the conventional material used in nitride-based SONOS devices, exhibits improvement of memory erasing characteristics and causes of the performance enhancement will be investigated. This thesis discusses several strategies to overcome challenges that SONOStype discrete charge storage nonvolatile memory currently faces. In conclusion, novel device structures, in addition to new materials such as high-¿ dielectrics and high work function metal gates, are promising candidates that can potentially be integrated into memory devices. Devices with the nanowire channel structure show promise for future nonvolatile applications due to their improved performance.