A very high speed bandpass continous time sigma delta modulator for RF receiver front end A/D conversion

Abstract

A design and circuit implementation of a CMOS fourth-order continuous-time bandpass fs/4 Sigma-Delta modulator is presented. The modulator uses fully differential multi feedback architecture. A novel way of realizing the feedback architecture in circuit in order to overcome the problem of loop delay in the modulator is proposed. Simulation results comparing the conventional architecture and the proposed one are also reported. To realize the bandpass filters, integrated LC resonators with active Q enhancement is used. A very high frequency transconductor is used to driving the bandpass LC resonators. Dynamic comparators are used to quantize the signal and the output is shaped to a return to zero, half return to zero waveform. The feedback occurs in current domain with the current from the switched current source DACs and that from the transconductor. The modulator, designed for 0.18 micrometer/1.8V 1P6M CMOS process occupies a total area of 1.8 sqr.mm. dissipating 290mW from a 1.8V power supply. At a sampling rate of 4GHz and a signal of 1GHz with 500 kHz bandwidth, the circuit achieves a peak Signal-to-Noise and Distortion Ratio (SNDR) of 40dB. With the proposed architecture the loop delay is keep below 3% of the clock period. The proposed architecture is also put under test for higher sampling frequencies to prove its stability.