Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/15915
Title: Design methodologies for instruction-set extensible processors
Authors: PAN YU
Keywords: ASIPs, instruction-set extensions, subgraph enumeration algorithm, worst case execution time, adaptive architectures, performance optimization
Issue Date: 8-Apr-2009
Source: PAN YU (2009-04-08). Design methodologies for instruction-set extensible processors. ScholarBank@NUS Repository.
Abstract: By integrating custom functional units (CFU) in parallel with standard ALUs in the processor core, the processor can be configured to accelerate different applications. A single custom instruction encapsulates a frequently occurring computation pattern involving multiple primitive operations. Parallelism and logic optimization among these operations can be exploited to implement the CFU, which leads to improved performance, compact code size, reduced register pressure, and improved overall energy efficiency. In this thesis, we first propose efficient and scalable subgraph enumeration algorithms for candidate custom instructions. Through exhaustive enumeration, isomorphic subgraphs embedded inside the dataflow graphs, which can be covered by the same custom instruction, are fully exposed. Second, we conduct a systematic study of the effects and correlations between various design constraints and system performance on a broad range of embedded applications. This study provides a valuable reference for the design of general extensible processors. Finally, we apply our methodologies in the context of real-time systems, to improve the worst-case execution time of applications using custom instructions.
URI: http://scholarbank.nus.edu.sg/handle/10635/15915
Appears in Collections:Ph.D Theses (Open)

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