Simulation, modelling and fabrication of novel devices with steep subthreshold slope

Abstract

CMOS device scaling faces several fundamental limits. Non-scalability of the subthreshsold swing and adverse short channel effects like drain-induced barrier lowering, and band-to-band tunneling have led to high off-state leakage current. Thus, the impact-ionization MOS (I-MOS) transistor and tunneling field-effect transistor (TFET) have been explored as an alternative switching device for sub-60 mV/decade subthreshold swing. This work is devoted to addressing the issue of the non-scalability of the subthreshold swing.For the I-MOS technology, process and device design innovations like the double-spacer I-MOS were applied to achieve excellent device performance with good short channel effects. The employment of SiGe in SiGe complementary I-MOS further reduces the power supply voltage requirement, while boosting the device performance in terms of off-state and on-state current. For compactness and better scalability, an I-MOS transistor with an elevated I-region or the L-shaped I-MOS transistor has been proposed as a promising candidate for enhanced performance through strain and materials engineering. Both I-MOS with an elevated Si1-yCy RSD and I-MOS with an elevated Si1-xGex RSD have been realized and proved to be viable not only in reducing the breakdown voltage, but also to enhance the performance further. An impact-ionization nanowire multiple-gate field-effect transistor (I-FinFET) was also proposed and fabricated, leading to a significant reduction in the source bias needed to sustain impact-ionization. In situ doping, strain and material engineering technology were employed for enhanced device performance. In addition, a simulation study on the Ge LI-MOS technology reveals promising potential.The TFET technology has been studied by extensive device simulation. A double-gate Si TFET with SiGe source was proposed and explored. Less than 60 mV/decade subthreshold swing with extremely low off-state leakage current is achieved by optimizing the device parameters and Ge content in the source. Power supply voltage scaling is projected to be possible with the introduction of much narrower bandgap material like Ge or InAs. Thus, low supply voltage coupled with bandgap engineering helps to pave the way for transistor downscaling while maintaining low power consumption.In summary, novel devices with steep subthreshold slope were proposed and studied. They reveal promising potential for augmenting the performance of conventional CMOS transistors.