Design of a correlator for UWB transceivers

Abstract

The thesis describes the design and implementation of a wideband analog correlator for UWB transceivers. The analog time integrating correlator consists of a transconductor based multiplier and a transconductor-C integrator. In order to increase the bandwidth of the multiplier, a pole-zero cancellation technique is proposed. Similar to the shunt-peaking technique, an inductor is added at the output of the multiplier. The simulation has shown that the bandwidth can be increased by 5 times from 2 GHz to 10 GHz. The transconductor in the integrator is implemented with a simple inverter that operates in the saturation region. The chip is fabricated in a commercial 0.18-I?m CMOS process and operates under a 1.8-V supply. The test results show that the correlator is able to operate with an input of 0.2-ns narrow monocycle pulse at 50-MHz repetition rate and produce a correct integrated output. The power consumption of the correlator is 13.6mW.