Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/15333
Title: The development of building block circuits for high-speed decimation filters
Authors: CHANDRASEKARAN RAJASEKARAN
Keywords: CMOS, Differential logic, Decimation filter, Full adder, Flip-Flop, RF digitization
Issue Date: 17-Jul-2006
Source: CHANDRASEKARAN RAJASEKARAN (2006-07-17). The development of building block circuits for high-speed decimation filters. ScholarBank@NUS Repository.
Abstract: Direct digitization of the RF input signal requires an A/D converter that can operate at a high sampling frequency, usually a multiple of the RF carrier frequency. To reduce the complexity of circuits functioning at such a high frequency, more functions are shifted to the digital domain that is more robust. In the case of oversampling A/D converters, the digital domain usually consists of a decimation filter that reduces the sampling rate to Nyquist rate. This necessitates the design of circuit components like arithmetic circuits that can function at RF frequencies. The circuits have to occupy a small area and consume a low power as well because the filter will require several components for its construction.The design of high-speed digital circuits a?? a full adder cell and a flip-flop a?? that can be used in a decimation filter for direct RF digitization analog-digital converter is the main objective of the research. The circuits have been implemented in a 0.18 A?m/1.8 V 1P6M CMOS process. The chip occupies an area of 1 mmA? and includes separate test structures for the filter and the individual full adder and flip-flop circuits. The test plan and the measurement results for the above have been detailed. The test results have been analyzed and suggestions for future improvements are presented.
URI: http://scholarbank.nus.edu.sg/handle/10635/15333
Appears in Collections:Master's Theses (Open)

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