Metal gate with high-K dielectric in Si CMOS processing

Abstract

As CMOS devices continue to be scaled down, conventional polysilicon gate and conventional silicon oxide dielectric will encounter problems such as poly depletion, high resistivity, and high gate leakage current. High-K dielectrics and metal gate have been studied widely to solve the above problems. However, the poor compatibility of high-K dielectric with polysilicon gate and the integration of metal gates for Si CMOS technology are still big challenges. The aim of this study was to evaluate the feasibility of new approaches for integrating dual metal gates and their compatibility with the conventional Si CMOS process. Four different new methods for integrating metal gates, namely, new metal alloys using thin AlN buffer layer, FUSI HfSi gate, substituted Al metal gate, and FUSI PtxSi gate were proposed and demonstrated. Another objective of this study was to improve thermal stability and carrier mobility using top surface nitrided and aluminized high-K stack, which is HfAlON/HfO2.