LOW-POWER MANY-CORE ARCHITECTURES FOR THE NEXT GENERATION WEARABLES

Abstract

Wearable devices are now leveraging power-efficient processors inside the SoC (System-on-Chip) to cater to the increasing computational demands of the wearable applications, such as real-time response. Many-core architectures enable improved performance by exploiting the available thread-level parallelism in many wearable applications but suffer from high power consumption that is crucial in the wearable domain with stringent power budget. In addition, the power-efficiency can be effectively improved using application-specific ASIC accelerators. However, it is not practical or feasible to design an accelerator for each wearable application starting from scratch due to the prohibitively high non-recurring engineering (NRE) cost and exacting time-to-market constraints. In this dissertation, we focus on novel customizable many-core architecture designs to enable high performance/watt for the next generation wearables.