Reliability modeling of ultra-thin gate oxide and high-k dielectrics for nano-scale CMOS devices

Abstract

As complementary metal-oxide semiconductor (CMOS) technology is scaled to the critical dimensions regime of several tens of nanometer, gate oxide thickness is progressively reduced from thick to thin oxide (< 20??), ultra-thin (<15??) and eventually to high-K dielectrics. In the process, oxide degradation mechanism is changed. In this thesis, the breakdown mechanisms for oxides with thickness ranging from 13?? to 45?? are examined. Various mechanisms are described and investigated, including quasi-breakdown, interface trap enhanced tunneling (ITET) and progressive breakdown. Eventually, high-K dielectrics will be required for continual gate dielectric scaling. The reliability for high-K stacks is examined and a novel technique for stack reliability is proposed and experimentally tested.