STT-MRAMS CIRCUIT TECHNIQUES FOR ENHANCED ROBUSTNESS IN LOW POWER EMBEDDED APPLICATIONS

Abstract

This thesis focuses on different circuit techniques to address major issues in STT-MRAMs. To mitigate high write energy, a comprehensive study on applying dynamic voltage scaling on STT-MRAM was conducted. Minimum-energy operations of STT-MRAM was first explained and examined in detail. To enhance the read robustness, three novel sensing techniques are proposed. The first technique amplifies the bitline voltage to increase the read sensing margin by adopting a low-overhead switched-cap booster. The second technique dynamically adjusts the reference based on bitcell state to increase the sensing margin. This technique is orthogonal to the first approach, hence, they can be jointly adopted. The third technique is the first-ever time-based sensing scheme where the read operation is performed in the time domain without the need of analog reference and sense amplifier. All proposed sensing schemes can achieve commercial-standard memory yield (1E-9 bit-error-rate) under strict constraints of the read current.