Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/13956
Title: Automatic mapping of statechart into verilog
Authors: TRAN VU VIET ANH
Keywords: Statecharts, Verilog, embedded system, hardware/software co-specification
Issue Date: 26-May-2004
Source: TRAN VU VIET ANH (2004-05-26). Automatic mapping of statechart into verilog. ScholarBank@NUS Repository.
Abstract: It is an established connection and a mapping system between Statecharts and Verilog programming language. As we known, Statecharts is a powerful visual formalism for specifying discrete event systems and it is a significant specification language. Statecharts diagrams represent the behavior of entities capable of dynamic behavior by specifying its response to the receipt of event instances. Nowadays, Verilog is widely used language for hardware description in industry. There are number of works to explore and to develop Verilog. However, the translation from Statecharts to Verilog is still not complete yet. In this work, we also investigated a system to map a source Statecharts into a target Verilog and to correlate between them. We demonstrate our work through an implemented system and some examples. The Implementation is divided into two parts; Statecharts editor and mapping program. The editor, we called Statechart_E, it is a stencil has built to add-on the Microsoft Visio 2002. The mapping program, we called AMSV (Automatic Mapping of Statechart into Verilog), it is written in Java to implement the mapping algorithm.
URI: http://scholarbank.nus.edu.sg/handle/10635/13956
Appears in Collections:Master's Theses (Open)

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