Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/13931
Title: If sampling receiver front end design
Authors: SU ZHENJIANG
Keywords: IF sampling, analog-to-digital conversion, bandpass sigma-delta modulation, switched-capacitor, track&hold, intermediate frequency
Issue Date: 19-Jul-2004
Source: SU ZHENJIANG (2004-07-19). If sampling receiver front end design. ScholarBank@NUS Repository.
Abstract: A high speed CMOS IF sampling receiver for digital wireless application is described in this thesis. The receiver consists of a continuous-time IF amplifier, a subsampling switched-capacitor gain stage and a fourth-order bandpass sigma-delta A/D converter. Due to its IF sampling nature, the receiver is highly immune to dc offset, flicker noise and errors due to mismatches between I and Q signal paths. The receiver is implemented in a 0.6um, double-poly, triple-mental CMOS process, and operated from a 3.3-V power supply. For a 210-MHz input signal, the measured result show that the receiver can achieve a 48-dB dynamic range over a 200kHz bandwith centered at 10MHz when sampled at 40MHz. The power dissipation of the receiver is 69.3mW.
URI: http://scholarbank.nus.edu.sg/handle/10635/13931
Appears in Collections:Master's Theses (Open)

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