PARTIALLY RECONFIGURABLE HETEROGENEOUS MULTI-PROCESSOR SYSTEMS ON-CHIP

Abstract

FPGA-based Heterogeneous Multiprocessor Systems-on-Chip (HMPSoCs) are becoming popular for high performance embedded systems because of their powerful computational ability and flexible architecture to adapt to unexpected changes. However, with the insatiable demands of supporting an extensive range of applications beyond the limited resources of FPGA chip and shorter time-to-market, partially reconfigurable (PR) FPGA architectures turn out to be the promising solutions. The ultimate objective of this thesis is to facilitate the PR design process by providing a flexible framework with design automation tools. The researchers and engineers are free to focus more on high-level system optimizations and application implementations to widen the adoption of PR in the FPGA design world.