Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/13674
Title: Design and development of a CMOS power amplifier for digital applications
Authors: KHOO EE SZE
Keywords: power amplifier, CMOS, class AB, load-pull, temeperature compensation circuit, cascode structure
Issue Date: 19-Mar-2004
Source: KHOO EE SZE (2004-03-19). Design and development of a CMOS power amplifier for digital applications. ScholarBank@NUS Repository.
Abstract: The IC technology for RFIC circuits continues to change as performance; cost and time to market are the three major factors that influence the choice of technology used. At present, GaAs, Silicon Bipolar and BiCMOS technologies constitute major portion of the RF market. However, CMOS technology, which supported by enormous momentum of the digital market have achieved higher transit frequencies in sub-micron region. Hence, it is viable now to integrate the RF portion in a single or even with digital circuits in future. In this thesis, issues of implementing RF circuits in CMOS technology like substrate coupling, low Q passive components, low breakdown voltage, hot carrier effects, parameter variations with temperature and process, low current capabilities of metal layers will be discussed in details. The main focus of this thesis will be the design and implementation of a 2.45GHz CMOS Power Amplifier. The models used in designing the power amplifier will be shown. The practical aspects of the implementation of the circuit will be highlighted. Methods are proposed to overcome some of the issues mentioned above. A cascade output stage structure is used to solve the hot carrier effects and low breakdown voltage issues. Temperature dependent biasing circuit is used in the design. The simulation results of the design and measurement results of the fabricated die will be presented.
URI: http://scholarbank.nus.edu.sg/handle/10635/13674
Appears in Collections:Master's Theses (Open)

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