Circuit performance and yield optimization with worst-case and Monte Carlo analyses

Abstract

This paper proposes a methodology for analog circuit performance and production yield optimization with the assistance of worst-case analysis and Monte Carlo simulation. Experimental results with a new commercial circuit is presented. Compared with the initial circuit, our optimized circuit is much more stable and has almost 100% predicted yield. Our work shows that Monte Carlo analysis can provide useful information to guide a designer in determining the nominal values as well as tolerance of circuit components so that an optimal design and required production yield can be obtained.