Chui, K.-J.Ang, K.-W.Madan, A.Wang, H.Tung, C.-H.Wong, L.-Y.Wang, Y.Choy, S.-F.Balasubramanian, N.Li, M.F.Samudra, G.Yeo, Y.-C.ELECTRICAL & COMPUTER ENGINEERING2014-10-072014-10-072005Chui, K.-J.,Ang, K.-W.,Madan, A.,Wang, H.,Tung, C.-H.,Wong, L.-Y.,Wang, Y.,Choy, S.-F.,Balasubramanian, N.,Li, M.F.,Samudra, G.,Yeo, Y.-C. (2005). Source/drain germanium condensation for P-channel strained ultra-thin body transistors. Technical Digest - International Electron Devices Meeting, IEDM 2005 : 493-496. ScholarBank@NUS Repository.078039268X01631918https://scholarbank.nus.edu.sg/handle/10635/84207This paper reports a novel technique to fabricate uniaxial compressive strained P-channel transistors with Silicon-Germanium (SiGe) source and drain (S/D) Stressors. The process involves local Ge condensation of a selectively grown SiGe region, thus driving Ge into and enriching the Ge concentration in the source and drain regions adjacent to the transistor channel. The process is particularly suitable for ultra-thin-body (UTB) transistors since it eliminates the need for a Si recess etch prior to SiGe epitaxy. In addition, the required thermal budget for Ge condensation is not prohibitive for UTB structures. High Ge mole fraction could be achieved in the S/D regions, leading to higher strain levels in the transistor channel. We demonstrate the feasibility of this technique in Silicon-on-Insulator (SOI) P-MOSFETs with a gate length L G of 90 nm. Drive current IDsat enhancement of up to 35% was observed. © 2005 IEEE.Conference PaperNOT_IN_WOS