ScholarBank@NUShttps://scholarbank.nus.edu.sgThe DSpace digital repository system captures, stores, indexes, preserves, and distributes digital research material.Thu, 27 Jun 2019 10:17:26 GMT2019-06-27T10:17:26Z501351- Design of discrete-coefficient FIR filters on loosely connected parallel machineshttps://scholarbank.nus.edu.sg/handle/10635/55576Title: Design of discrete-coefficient FIR filters on loosely connected parallel machines
Authors: Lim, Y.C.; Sun, Y.; Yu, Y.J.
Abstract: This paper presents a new branch-and-bound mixed-integer linear programming-based algorithm for designing discrete-coefficient finite-impulse response (FIR) filters using a cluster of workstations as the computation platform. The discrete coefficient space considered in this paper is the sum of signed power-of-two space, but the technique is also applicable to other discrete coefficient spaces. The key issue determining the success of the algorithm is the ability to partition the original problem into several independent parts that can be distributed to a cluster of machines for solution. The master-slave model is adopted for the control of the machines. Test run results showed that super linear speedup (i.e., the speedup factor is more than the number of machines running in parallel) may be achieved.
Sat, 01 Jun 2002 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/555762002-06-01T00:00:00Z
- Fast vicinity-upgrade algorithm for rectilinear Steiner treeshttps://scholarbank.nus.edu.sg/handle/10635/80418Title: Fast vicinity-upgrade algorithm for rectilinear Steiner trees
Authors: Chua, J.K.; Lim, Y.C.
Abstract: A new algorithm for rectilinear Steiner trees (RST) is presented. The proposed algorithm is based on successively constructing a vicinity structure from a rectilinear minimum spanning tree (MST) and generating a refined RST. The algorithm achieves an 8.5-10% average cost improvement over the rectilinear MST at a time complexity of O(n log n). To address specifically the linear programming approach of global routing, the algorithm is modified to generate K trees.
Tue, 01 Jan 1991 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/804181991-01-01T00:00:00Z
- Grid density for design of one- and two-dimensional FIR filtershttps://scholarbank.nus.edu.sg/handle/10635/80507Title: Grid density for design of one- and two-dimensional FIR filters
Authors: Yang, R.H.; Lim, Y.C.
Abstract: The frequency response of a digital filter is often optimised to meet a given set of specifications on a dense grid of frequency points. The density of the frequency grid points must be sufficiently high so that the frequency response of the filter does not violate the specifications at frequencies in between the grid points. However, the computational complexity of the design process and the storage requirements of the computer increase with the number of frequency grid points. In this a detail study of the grid density requirement for the design of FIR filters is presented. The study leads to a useful design rule.
Tue, 01 Jan 1991 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/805071991-01-01T00:00:00Z
- NEW PIPELINED VECTOR-REDUCTION ARITHMETIC UNIT FOR FIR FILTER IMPLEMENTATION.https://scholarbank.nus.edu.sg/handle/10635/80807Title: NEW PIPELINED VECTOR-REDUCTION ARITHMETIC UNIT FOR FIR FILTER IMPLEMENTATION.
Authors: Lim, Y.C.
Abstract: In realizing an N-tap finite impulse-response (FIR) filter, N multiplications and N-1 additions must be performed during every sampling interval. The multiplication process can be pipelined easily because there is no recurrence. The (N-1)-port addition process is essentially a vector-reduction process with inherent recurrence and is a bottleneck of hardware utilization when implemented using a pipelined arithmetic unit. We present a new pipeline structure of implementing the multiport adder. For an arithmetic pipeline with M segments, our new design achieves the theoretical upper bound on hardware utilization provided that N greater than equivalent to (L plus 2)M minus 2**L** plus **1 where L equals Int (log//2(M)), the largest integer less than or equal to log**2(M). This pipeline structure is also useful in pipelined signal-processor design.
Wed, 01 Jul 1987 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/808071987-07-01T00:00:00Z
- Optimum design of one and two-dimensional FIR filters using the frequency response masking techniquehttps://scholarbank.nus.edu.sg/handle/10635/80919Title: Optimum design of one and two-dimensional FIR filters using the frequency response masking technique
Authors: Lim, Y.C.; Lian, Yong
Abstract: In the frequency response masking technique, the impulse response of a prototype filter and that of its complement are up-sampled (by inserting zeros) by a factor of M and then cascaded to a pair of interpolators. The prototype filter itself may again be synthesized using the frequency response masking technique producing a multistage frequency response masking design. In this paper, we derive an expression for the impulse response up-sampling ratio M, which will produce a minimum complexity design. We show that 1) M approaches e (the base of the natural algorithm) as the number of frequency response masking stages increases, 2) in a K-stage design the complexity of the filter is inversely proportional to the (K+1)th root of the transition width, 3) the frequency response masking technique is effective if the normalized transition width is less then 1/16, and 4) the frequency response masking technique is more efficient than the interpolated impulse response technique if the square root of the normalized transition width is less than the arithmetic mean of the normalized passband edge and stopband edge. We also derive an expression for the multistage frequency response ripple compensation. An optimum design relationship for the interpolated impulse response technique is also derived. The design of narrow-band two-dimensional filters using the frequency response masking technique is also presented.
Mon, 01 Feb 1993 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/809191993-02-01T00:00:00Z
- NEW HIGH PERFORMANCE TWO-PHASE CLOCK GENERATION CIRCUITS.https://scholarbank.nus.edu.sg/handle/10635/80803Title: NEW HIGH PERFORMANCE TWO-PHASE CLOCK GENERATION CIRCUITS.
Authors: Lim, Y.C.; Ko, C.C.; Singh, H.
Abstract: Two high performance two-phase non-overlapping clock generation circuits are presented. These circuits are suitable for generating control clock signals for switched capacitor filters and pipelined digital hardware.
Tue, 01 Jul 1986 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/808031986-07-01T00:00:00Z
- New prefilter structure for designing filtershttps://scholarbank.nus.edu.sg/handle/10635/80809Title: New prefilter structure for designing filters
Authors: Lian, Y.; Lim, Y.C.; Lim, Y.C.
Abstract: A new prefilter structure is presented. The frequency response of the prefilter structure is derived from the combination of two cosine functions. By cascading these prefilters with an appropriate equalizer, low complexity filters with high stopband attenuation can be achieved. The proposed prefilter leads to a significant saving in the number of arithmetic operations in the prefilter-equalizer cascade structure.
Fri, 01 Jan 1993 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/808091993-01-01T00:00:00Z
- NEW PUSH-PULL CIRCUIT USING IDENTICAL VMOS TRANSISTORS.https://scholarbank.nus.edu.sg/handle/10635/80810Title: NEW PUSH-PULL CIRCUIT USING IDENTICAL VMOS TRANSISTORS.
Authors: Lim, Y.C.; Ko, C.C.
Abstract: A new audio push-pull circuit using identical VMOS power transistors is presented. The design produces well matched positive and negative cycles open loop amplification. Phase splitting is implicit in the design, rendering phase split driver unnecessary. Comparing to the conventional designs, this new design has the advantage of circuit simplicity while preservng the linearity.
Wed, 01 Jan 1986 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/808101986-01-01T00:00:00Z
- FPGA implementation of digital filters synthesized using the FRM techniquehttps://scholarbank.nus.edu.sg/handle/10635/56085Title: FPGA implementation of digital filters synthesized using the FRM technique
Authors: Lim, Y.C.; Yu, Y.J.; Zheng, H.Q.; Foo, S.W.
Abstract: The effective length of a filter designed using the frequency-response masking (FRM) technique is very long and requires a very large number of delay elements. In this paper, we present some useful techniques for reducing the data transfer between the field programmable gate array (FPGA) and external memory when the random logic is implemented using the FPGA and the delay elements are implemented using an external memory such as dynamic random access memory.
Sat, 01 Mar 2003 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/560852003-03-01T00:00:00Z
- Frequency grid density for the design of 2-D FIR filtershttps://scholarbank.nus.edu.sg/handle/10635/80456Title: Frequency grid density for the design of 2-D FIR filters
Authors: Low, S.H.; Lim, Y.C.
Abstract: In the design of a digital 2-D FIR filter, the frequency response is often optimised to satisfy a given set of specifications on a dense grid of frequency points. The accuracy of a filter design improves when there are more grid points, but this is at the expense of higher computational resources. The authors present the relationship between the accuracy and the frequency grid density in 2-D filter designs. A new formula for determining the frequency grid spacing is also proposed.
Thu, 01 Aug 1996 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/804561996-08-01T00:00:00Z
- Frequency-response masking approach for digital filter design: complexity reduction via masking filter factorizationhttps://scholarbank.nus.edu.sg/handle/10635/80460Title: Frequency-response masking approach for digital filter design: complexity reduction via masking filter factorization
Authors: Lim, Y.C.; Lian, Yong
Abstract: It has been reported in several recent publications that the frequency response masking technique is eminently suitable for synthesizing filters with very narrow transition-width. The major advantages of the frequency response masking approach are that the resulting filter has a very sparse coefficient vector and that the resulting filter length is only slightly longer than that of the theoretical (Remez) minimum. The system of filters produced by the frequency response masking technique consists of a sparse coefficient filter with periodic frequency response and one or more pairs of masking filters. Each pair of the masking filters consist of two filters whose frequency responses are similar except at frequencies near the band-edges. In this paper, we present three methods for reducing the complexity of the masking filters. The success of our technique is due to the fact that each pair of the masking filters can be realized as a cascade of a common subfilter and a pair of equalizers.
Mon, 01 Aug 1994 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/804601994-08-01T00:00:00Z
- Frequency-domain modeling of continuous-time systems using the lattice algorithms.https://scholarbank.nus.edu.sg/handle/10635/80459Title: Frequency-domain modeling of continuous-time systems using the lattice algorithms.
Authors: Lim, Y.C.; Parker, S.R.
Abstract: Two frequency-domain methods for modeling continuous-time system using the lattice algorithms are presented. In one of the methods, the frequency-domain data are sampled at a nonuniformly spaced frequency grid. This method is suitable for applications where the frequency response of the continuous-time systems can be measured explicitly. In the other method, the frequency-domain data are sampled at a uniformly spaced frequency grid. This method is suitable for applications where the frequency spectrum of the input and output signals are computed from the input and output time-domain data using the FFT (fast Fourier transform).
Wed, 01 Mar 1989 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/804591989-03-01T00:00:00Z
- FREQUENCY-RESPONSE MASKING APPROACH FOR THE SYNTHESIS OF SHARP LINEAR PHASE DIGITAL FILTERS.https://scholarbank.nus.edu.sg/handle/10635/80461Title: FREQUENCY-RESPONSE MASKING APPROACH FOR THE SYNTHESIS OF SHARP LINEAR PHASE DIGITAL FILTERS.
Authors: Lim, Yong Ching
Abstract: If each delay element of a linear-phase, low-pass digital filter is replaced by M delay elements, an (M plus 1)-band filter is produced. The transition-width of this (M plus 1)-band filter is 1/M that of the prototype low-pass filter. A complementary filter can be obtained by subtracting the output of the (M plus 1)-band filter from a suitably delayed version of the input. The complementary filter is an (M plus 1)-band filter whose passbands and stopbands are the stopbands and passbands, respectively, of the original (M plus 1)-band filter. If the frequency responses of the original (M plus 1)-band filter and its complementary filter are properly masked and recombined, a narrow transition-band filter can be obtained. This techniques can be used to design sharp low-pass, high-pass, bandpass, and bandstop filters with arbitrary passband bandwidth.
Tue, 01 Apr 1986 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/804611986-04-01T00:00:00Z
- Frequency-response masking approach for the synthesis of sharp two-dimensional diamond-shaped filtershttps://scholarbank.nus.edu.sg/handle/10635/80462Title: Frequency-response masking approach for the synthesis of sharp two-dimensional diamond-shaped filters
Authors: Lim, Y.C.; Low, S.H.
Abstract: The frequency-response masking (FRM) technique is an efficient method for realizing sharp one-dimensional (1-D) filters. Sharp 1-D filters realized using the FRM technique have considerably lower complexity than those realized in the direct form. In this paper, we present an extension of the FRM technique to the synthesis of sharp two-dimensional (2-D) diamondshaped (DS) filters. The new technique, based upon dividing the frequency spectrum into four complementary components and the utilization of four masking filters, achieves large reductions in filter implementation complexity when the transition width of the desired DS filter is very narrow. An expression for the impulse response up-sampling ratio that produces the design with the least complexity is derived. Extensions of the technique for the synthesis of 2-D filters other than the DS filters are also discussed. © 1998 IEEE Publisher Item Identifier S 1057-7130(98)08504-8.
Thu, 01 Jan 1998 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/804621998-01-01T00:00:00Z
- New filtering scheme for split-band voice codinghttps://scholarbank.nus.edu.sg/handle/10635/80801Title: New filtering scheme for split-band voice coding
Authors: Lim, Y.C.; Koh, S.N.; Ko, C.C.
Abstract: This paper presents a new filtering scheme for spliting speech signals into sub-bands which results in no aliasing problem when the sub-band signals are sub-sampled and recombined. The high-pass and low-pass filters are an odd-length complementary linear phase filter pair. As a consequence, the high-pass output can be obtained by subtracting the low-pass filter output from the appropriately delayed input. This produces a factor-of-two reduction in the computation load when compared to the conventional even-length quadrature mirror filter. Another factor-of-two saving in computation load can be gained by using half-band low-pass filters whose every other coefficient is zero. Furthermore, the filters can be designed using well-known minimax optimisation techniques such as the Remez exchange algorithm and integer programming.
Wed, 01 Mar 1989 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/808011989-03-01T00:00:00Z
- Grid density for design of one- and two-dimensional FIR filtershttps://scholarbank.nus.edu.sg/handle/10635/62263Title: Grid density for design of one- and two-dimensional FIR filters
Authors: Yang, R.H.; Lim, Y.C.
Abstract: The frequency response of a digital filter is often optimised to meet a given set of specifications on a dense grid of frequency points. The density of the frequency grid points must be sufficiently high so that the frequency response of the filter does not violate the specifications at frequencies in between the grid points. However, the computational complexity of the design process and the storage requirements of the computer increase with the number of frequency grid points. In this a detail study of the grid density requirement for the design of FIR filters is presented. The study leads to a useful design rule.
Tue, 01 Jan 1991 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/622631991-01-01T00:00:00Z
- Forward-backward LMS adaptive line enhancerhttps://scholarbank.nus.edu.sg/handle/10635/62210Title: Forward-backward LMS adaptive line enhancer
Authors: Lim, Y.C.; Ko, C.C.
Abstract: A new LMS (least-mean-square) adaptive line enhancer algorithm is presented. It makes use of forward and backward prediction errors to update the coefficient values. For a given feedback factor, the algorithm converges to the optimal Wiener solution with the same speed as for the LMS algorithm, but requires about twice the number of multiplications and additions. However, in the situation when the order of the enhancer is at least a few times larger than the number of sinusoids to be enhanced, or when the frequencies of the sinusoids to be enhanced are not close to 0 or 0.5, the misadjustment of the new algorithm is approximately half that of the LMS algorithm.
Sun, 01 Jul 1990 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/622101990-07-01T00:00:00Z
- Structure for narrow and moderate transition band FIR filter designhttps://scholarbank.nus.edu.sg/handle/10635/62822Title: Structure for narrow and moderate transition band FIR filter design
Authors: Lian, Y.; Lim, Y.C.
Abstract: A new structure, suitable for implementing narrow as well as moderately wide transition band FIR filters, is presented. The proposed structure leads to a saving of 20-40% in the number of multipliers for moderately wide transition band filters. The saving for the narrow transition band filter increases with decreasing transition width.
Thu, 08 Jan 1998 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/628221998-01-08T00:00:00Z
- Single-precision multiplier with reduced circuit complexity for signal processing applicationshttps://scholarbank.nus.edu.sg/handle/10635/62785Title: Single-precision multiplier with reduced circuit complexity for signal processing applications
Authors: Lim, Y.C.
Abstract: When two numbers are multiplied, a double-wordlength product is produced. In applications where only the single-precision product is required, the double-wordlength result is rounded to single-precision. Hence, in single-precision applications, it is not necessary to compute the least significant part of the product exactly. Instead, it is only necessary to estimate the carries generated in the computation of the least significant part that will ripple into the most significant part of the product. This will produce a single-precision multiplier with significantly reduced circuit complexity. Three novel methods for realizing this class of reduced complexity single-precision multipliers are introduced and their performance analyzed.
Thu, 01 Oct 1992 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/627851992-10-01T00:00:00Z
- Self-timed system design techniquehttps://scholarbank.nus.edu.sg/handle/10635/62747Title: Self-timed system design technique
Authors: Tan, Y.K.; Lim, Y.C.
Abstract: A new technique for the design of self-timed systems using a modified PCVSL (Precharged Cascode Voltage Switch Logic) circuit and a new handshaking protocol is presented. Our technique allows different data to be stored and computed in consecutive PCVSL pipeline stages simultaneously, resulting in a significant saving in silicon area and speed-up in fall-through delay.
Thu, 01 Mar 1990 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/627471990-03-01T00:00:00Z
- Signed power-of-two term allocation scheme for the design of digital filtershttps://scholarbank.nus.edu.sg/handle/10635/62762Title: Signed power-of-two term allocation scheme for the design of digital filters
Authors: Lim, Y.C.; Yang, R.; Li, D.; Song, J.
Abstract: It is well known that if each coefficient value of a digital filter is a sum of signed power-of-two (SPT) terms, the filter can be implemented without using multipliers. In the past decade, several methods have been developed for the design of filters whose coefficient values are sums of SPT terms. Most of these methods are for the design of filters where all the coefficient values have the same number of SPT terms. It has also been demonstrated recently that significant advantage can be achieved if the coefficient values are allocated with different number of SPT terms while keeping the total number of SPT terms for the filter fixed. In this paper, we present a new method for allocating the number of SPT terms to each coefficient value. In our method, the number of SPT terms allocated to a coefficient is determined by the statistical quantization step-size of that coefficient and the sensitivity of the frequency response of the filter to that coefficient. After the assignment of the SPT terms, an integer-programming algorithm is used to optimize the coefficient values. Our technique yields excellent results but does not guarantee optimum assignment of SPT terms. Nevertheless, for any particular assignment of SPT terms, the result obtained is optimum with respect to that assignment.
Fri, 01 Jan 1999 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/627621999-01-01T00:00:00Z
- Journal of Circuits, Systems and Computers: Guest editorialhttps://scholarbank.nus.edu.sg/handle/10635/68558Title: Journal of Circuits, Systems and Computers: Guest editorial
Authors: Lim, Y.C.
Wed, 01 Oct 2003 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/685582003-10-01T00:00:00Z
- Reducing the complexity of frequency response masking filters using half-band filtershttps://scholarbank.nus.edu.sg/handle/10635/81074Title: Reducing the complexity of frequency response masking filters using half-band filters
Authors: Lian, Y.; Lim, Y.C.
Abstract: The frequency-response masking approach provides an efficient realization for very sharp FIR filters with arbitrary bandwidth. In this paper, we introduce a method which uses a half-band filter to serve as one of the masking filters to achieve further saving in the number of multipliers. © 1995.
Wed, 01 Mar 1995 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/810741995-03-01T00:00:00Z
- Self-timed system design techniquehttps://scholarbank.nus.edu.sg/handle/10635/81145Title: Self-timed system design technique
Authors: Tan, Y.K.; Lim, Y.C.
Abstract: A new technique for the design of self-timed systems using a modified PCVSL (Precharged Cascode Voltage Switch Logic) circuit and a new handshaking protocol is presented. Our technique allows different data to be stored and computed in consecutive PCVSL pipeline stages simultaneously, resulting in a significant saving in silicon area and speed-up in fall-through delay.
Thu, 01 Mar 1990 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/811451990-03-01T00:00:00Z
- Improved weighted least squares algorithm for the design of quadrature mirror filtershttps://scholarbank.nus.edu.sg/handle/10635/80584Title: Improved weighted least squares algorithm for the design of quadrature mirror filters
Authors: Goh, C.-K.; Lim, Y.C.; Ng, C.S.
Abstract: This paper presents an improved weighted least squares (WLS) algorithm for the design of quadrature mirror filters (QMF's). First, a new term is incorporated into the objective function that effectively prevents an optimization algorithm from producing suboptimal QMF's. These suboptimal QMF's exhibit transition band anomaly; the frequency responses of the filters have large oscillatory components in the transition band. The new term can be applied to the WLS design of any FIR filter to prevent similar transition band anomaly. Next, we present the algorithm to obtain the QMF coefficients that minimizes the objective function incorporating the new term. The computational requirement of this algorithm is also briefly discussed. Last, we include a set of practical design rules for use with our algorithm. These rules simplify the design process by providing good estimation of the design parameters, such as the minimum filter length, to meet a given set of QMF specifications.
Fri, 01 Jan 1999 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/805841999-01-01T00:00:00Z
- Linearity improvement of CMOS transconductors for low supply applicationshttps://scholarbank.nus.edu.sg/handle/10635/80677Title: Linearity improvement of CMOS transconductors for low supply applications
Authors: Li, M.F.; Chen, X.; Lim, Y.C.
Abstract: A new CMOS transconductor circuit is proposed. It incorporates a current bootstrapping loop to improve the linearity without using a large source follower and high supply voltage.
Fri, 01 Jan 1993 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/806771993-01-01T00:00:00Z
- Signed power-of-two (SPT) term allocation scheme for the design of digital filtershttps://scholarbank.nus.edu.sg/handle/10635/50640Title: Signed power-of-two (SPT) term allocation scheme for the design of digital filters
Authors: Lim, Yong-Ching; Yang, Rui; Li, Dongning; Song, Jianjian
Abstract: It is well known that if each coefficient value of a digital filter is a sum of SPT terms, the filter can be implemented without using multipliers. In the past decade, several methods had been developed for the design of filters whose coefficient values are sums of SPT terms. Most of these methods are for the design of filters where all the coefficient values have the same number of SPT terms. In this paper, we present a new method for allocating different number of SPT terms to each coefficient value keeping the total number of SPT terms fixed. Our technique yields excellent results.
Thu, 01 Jan 1998 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/506401998-01-01T00:00:00Z
- Linear-phase digital audio tone control using multiplication-free FIR filterhttps://scholarbank.nus.edu.sg/handle/10635/80678Title: Linear-phase digital audio tone control using multiplication-free FIR filter
Authors: Lian, Yong; Lim, Yong Ching
Abstract: A new linear-phase FIR filter system for digital audio tone control applications is presented. The system is based on the multiplication-free fourth-order low-pass FIR filter. The arithmetic complexity of the system is very low. It only needs 24 summation operations per sample.
Fri, 01 Oct 1993 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/806781993-10-01T00:00:00Z
- LINEAR-PHASE DIGITAL AUDIO TONE CONTROL.https://scholarbank.nus.edu.sg/handle/10635/80679Title: LINEAR-PHASE DIGITAL AUDIO TONE CONTROL.
Authors: Lim, Y.C.
Abstract: A new linear-phase three-way filter system for digital audio tone-control application is presented. Approximately 80% of its coefficient values are zero. The remaining nonzero coefficient values are 0. 5 and 0. 25. Thus the filter system is essentially multiplication free. When the high-frequency and low-frequency gain weightings are unity, the filter system acts as a pure delay producing no frequency response distortion.
Thu, 01 Jan 1987 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/806791987-01-01T00:00:00Z
- Practical design rules for minimax linear phase diamond-shaped 2-d fir low-pass filtershttps://scholarbank.nus.edu.sg/handle/10635/81007Title: Practical design rules for minimax linear phase diamond-shaped 2-d fir low-pass filters
Authors: Lim, Y.C.
Abstract: Diamond-shaped filters are used as antialiasing filters in the conversion between images sampled on the rectangular and quincunx sampling grids. In this brief, we investigate some characteristics of the linear phase diamond-shaped low-pass filters and present a set of design rules applicable to the design of such filters optimal in the minimax error sense. The design rules provide good estimates for the minimum filter support size required to satisfy a given set of specifications. In most cases, the difference between the estimated minimum filter support size and the actual minimum filter support size is less than 5%. © 1997 IEEE.
Wed, 01 Jan 1997 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/810071997-01-01T00:00:00Z
- Signed power-of-two term allocation scheme for the design of digital filtershttps://scholarbank.nus.edu.sg/handle/10635/81160Title: Signed power-of-two term allocation scheme for the design of digital filters
Authors: Lim, Y.C.; Yang, R.; Li, D.; Song, J.
Abstract: It is well known that if each coefficient value of a digital filter is a sum of signed power-of-two (SPT) terms, the filter can be implemented without using multipliers. In the past decade, several methods have been developed for the design of filters whose coefficient values are sums of SPT terms. Most of these methods are for the design of filters where all the coefficient values have the same number of SPT terms. It has also been demonstrated recently that significant advantage can be achieved if the coefficient values are allocated with different number of SPT terms while keeping the total number of SPT terms for the filter fixed. In this paper, we present a new method for allocating the number of SPT terms to each coefficient value. In our method, the number of SPT terms allocated to a coefficient is determined by the statistical quantization step-size of that coefficient and the sensitivity of the frequency response of the filter to that coefficient. After the assignment of the SPT terms, an integer-programming algorithm is used to optimize the coefficient values. Our technique yields excellent results but does not guarantee optimum assignment of SPT terms. Nevertheless, for any particular assignment of SPT terms, the result obtained is optimum with respect to that assignment.
Fri, 01 Jan 1999 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/811601999-01-01T00:00:00Z
- Improved cross-coupled quad transconductor cellhttps://scholarbank.nus.edu.sg/handle/10635/114563Title: Improved cross-coupled quad transconductor cell
Authors: Lai, W.H.; Lim, Y.C.; Li, M.F.
Abstract: The addition of current feedback loops to the cross-coupled CMOS transconductor cell to reduce the quiescent currents while maintaining comparable linearity is described. The circuits were simulated in SPICE using BSIM models and a power supply of ±5 V. Denoting ε as linearity error, Vid as differential input signal and fc as cut-off frequency, |ε| < 1% for |Vid| < 1.3 V, fc = 130 MHz and static power consumption of 5.2 mW are obtained if the output is single-ended. If differential output is employed, |ε| < 0.6% for |Vid| < ±2.4 V, fc = 80 MHz and static power consumption of 6.1 mW are obtained. In both cases, the THD for a Vid = 1 Vpp at 1 kHz is 1.3%.
Wed, 01 Jan 1997 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/1145631997-01-01T00:00:00Z
- COMPLEMENTARY FILTERING TECHNIQUE FOR SUBBAND SPEECH CODER DESIGN.https://scholarbank.nus.edu.sg/handle/10635/72532Title: COMPLEMENTARY FILTERING TECHNIQUE FOR SUBBAND SPEECH CODER DESIGN.
Authors: Lim, Y.C.; Koh, S.N.; Ko, C.C.
Abstract: A filtering scheme for splitting speech signals into subbands which results in no aliasing problem when the subband signals are subsampled and recombined is presented. The highpass and lowpass filters are an odd-length complementary linear phase filter pair. As a consequence, the highpass filter output can be obtained by subtracting the lowpass filter output from the appropriately delayed input. This produces a factor-of-two reduction in the computation load when compared to the conventional even-length quadrature mirror filter. Another factor-of-two saving in computation load can be gained by using halfband lowpass filters whose every other coefficient is zero. Furthermore, the filters can be designed using well known minimax optimization techniques such as the Remez exchange algorithm and integer programming.
Thu, 01 Jan 1987 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/725321987-01-01T00:00:00Z
- DESIGN OF CASCADE FORM FIR FILTERS FOR DISCRETE SPACE IMPLEMENTATION.https://scholarbank.nus.edu.sg/handle/10635/72567Title: DESIGN OF CASCADE FORM FIR FILTERS FOR DISCRETE SPACE IMPLEMENTATION.
Authors: Lim, Y.C.; Liu, Bede
Abstract: When an FIR (finite-impulse response) filter with discrete valued coefficients is implemented in direct form, the peak of the amplitude response decreases with increasing filter length, but only up to certain length. Further reduction in peak ripple beyond that point cannot be realized easily without increasing the coefficient precision. It is shown that by cascading two direct-form FIR filters, each with coefficients that are sum or difference of two power-of-two terms, it is possible to achieve very small peak ripple.
Fri, 01 Jan 1988 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/725671988-01-01T00:00:00Z
- Efficient algorithm to design perfect reconstruction regular quadrature mirror filters using weighted Lp error criteriahttps://scholarbank.nus.edu.sg/handle/10635/81406Title: Efficient algorithm to design perfect reconstruction regular quadrature mirror filters using weighted Lp error criteria
Authors: Goh, Chee-Kiang; Lim, Yong-Ching
Abstract: An efficient iterative algorithm is presented in this paper to design lattice-type perfect reconstruction regular quadrature mirror filters (PR-QMF) by minimizing the pth power of an appropriate error criteria, where p can be a function of ω. The filter bank design is approximated as an unconstrained weighted least squares problem with respect to the lattice coefficients. Typically, only a few iterations of our algorithm is needed to obtain an optimal solution in the weighted Lp sense. An estimation of the number of canonic signed digit(CSD) terms needed to quantize the lattice coefficients yielding minimal degradation of the filter's stopband attenuation is also derived. Efficient multiplierless implementation of lattice-type regular PR-QMF banks are easily obtained using this result.
Thu, 01 Jan 1998 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/814061998-01-01T00:00:00Z
- Efficient algorithm to design quadrature mirror filters using multi-band weighted Lp error criteriahttps://scholarbank.nus.edu.sg/handle/10635/81407Title: Efficient algorithm to design quadrature mirror filters using multi-band weighted Lp error criteria
Authors: Goh, Chee-Kiang; Lim, Yong-Ching
Abstract: An efficient iterative algorithm is presented in this paper to design quadrature mirror filters by minimizing the p-th power of the error function, where p may varied in different frequency band. Our algorithm incorporates the iterative re-weighted least squares technique. The filter bank design is approximated as a weighted least-squares quadratic programming problem. Good designs are obtained typically in a few iterations. The algorithm designs quadrature mirror filters which satisfy mixed Lp error criteria in the overall filter bank frequency responses and the filters stop-band responses.
Mon, 01 Jan 1996 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/814071996-01-01T00:00:00Z
- CMOS low noise capacitance measurement circuit for micromachined gyroscopehttps://scholarbank.nus.edu.sg/handle/10635/72521Title: CMOS low noise capacitance measurement circuit for micromachined gyroscope
Authors: Yu, Wen; Lim, Yong Ching; Tay, Francis E.H.; Liang, Yung C.
Abstract: A CMOS low noise, high sensitivity circuit suitable for detecting the change in capacitance along the sensing direction of a vibrating gyroscope with interdigitated finger comb structure is presented. The circuit is used in conjunction with a fully differential capacitor bridge, which is formed by the sensing port of the mechanical structure. A mathematical model of a gyroscope is established for electrical simulation with electrical equivalent circuit. Theoretical analysis and computer simulations using HSPICE show that as low as 0.2aF change in capacitance is detectable under ideal condition. Two high frequency carriers of the same magnitude and frequency are used in the circuit. Simulation results review that the resolution of the technique is severely affected by the mismatch of the high frequency carriers. The effect of parasitic capacitance, which is inherent in the silicon micromachining technology, can be greatly reduced by selecting appropriate circuit configuration.
Fri, 01 Jan 1999 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/725211999-01-01T00:00:00Z
- Efficient algorithms for two and three-layer over-the-cell channel routinghttps://scholarbank.nus.edu.sg/handle/10635/72602Title: Efficient algorithms for two and three-layer over-the-cell channel routing
Authors: Shew, Paul-Waie; Yan, Jin-Tai; Hsiao, Pei-Yung; Lim, Yong-Ching
Abstract: We present a new efficient algorithm for both two and three-layer over-the-cell channel routing in the standard cell design technology. Our approach considers both density distribution in the channel and longest path in vertical constraint graph. Besides, we use vacant terminals to eliminate cycles in the vertical constraint graph as well as to reduce the maximum cliques in the horizontal constraint graph for selecting net segments to be routed over the cells. For the PRIMARY 1 benchmark examples, our router reduced the total channel height by 39.1% and 61.0% for two-layer and three-layer routing model, respectively.
Sat, 01 Jan 1994 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/726021994-01-01T00:00:00Z
- Efficient algorithm to design weighted minimax perfect reconstruction quadrature mirror filtershttps://scholarbank.nus.edu.sg/handle/10635/72601Title: Efficient algorithm to design weighted minimax perfect reconstruction quadrature mirror filters
Authors: Goh, Chee-Kiang; Lim, Yong-Ching
Abstract: An efficient algorithm is presented in this paper to design lattice-type perfect reconstruction quadrature mirror filters (PR-QMF). Our proposed iterative algorithm design the lattice coefficients of the filter bank directly, with flexible control of the filters' stop-band ripple profiles. Typically, only a few iterations of our algorithm is needed to converge to an optimal solution in the weighted minimax sense. A procedure to obtain the lattice coefficients of PR-QMF banks yielding near linear phase filters is presented.
Wed, 01 Jan 1997 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/726011997-01-01T00:00:00Z
- Constant offset sample-and-hold CMOS switching circuithttps://scholarbank.nus.edu.sg/handle/10635/72542Title: Constant offset sample-and-hold CMOS switching circuit
Authors: Yong, Y.K.; Li, M.F.; Lim, Y.C.; Yep, S.Y.
Abstract: A new CMOS switch circuit is proposed for the implementation of high precision sample-and-hold. The switch includes a current mirror and switching action is controlled by current pulses. This results in the offset voltage due to clock feedthrough to be input voltage independent. Thus, the constant offset can be easily compensated in subsequent stages.
Wed, 01 Jan 1997 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/725421997-01-01T00:00:00Z
- Reducing the complexity of FIR filters by using parallel structureshttps://scholarbank.nus.edu.sg/handle/10635/81708Title: Reducing the complexity of FIR filters by using parallel structures
Authors: Lian, Yong; Lim, Yong Ching
Abstract: A novel structure to implement narrow as well as moderately wide transition-width computationally efficient FIR filters is presented. The structure yields 20%-40% savings in the number of multipliers for moderately wide transition-width filters. The saving for the narrow transition-width filters increases with decreasing transition-width.
Fri, 01 Jan 1993 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/817081993-01-01T00:00:00Z
- Pipelined implementation of recursive filterhttps://scholarbank.nus.edu.sg/handle/10635/81677Title: Pipelined implementation of recursive filter
Authors: Lim, Yong Ching; Liu, Bede
Abstract: If the input to a pipeline depends on its previous output, poor hardware utilization can result because the required output is not immediately available. In a recursive filter, the output at the nth sampling instance, y(n), depends on its previous output, y(n-1). Thus, pipeline implementation of recursive filter may result in poor hardware utilization if the dependency problem is not resolved. This problem can be solved by substitution. However, unsuitable substitution can lead to instability. The stability of pipelined recursive filter is investigated, and substitution strategies that produce stable filters are presented. The use of complex conjugate pole-zero pairs is discussed, and roundoff noise is considered.
Sun, 01 Jan 1989 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/816771989-01-01T00:00:00Z
- Polynomial-time algorithm for designing digital filters with power-of-two coefficientshttps://scholarbank.nus.edu.sg/handle/10635/81678Title: Polynomial-time algorithm for designing digital filters with power-of-two coefficients
Authors: Li, Dongning; Song, Jianjian; Lim, Yong Ching
Abstract: This paper presents an algorithm for designing digital filters with coefficients expressible as sums of signed power-of-two (SPT) terms. For each filter gain, the time complexity of the algorithm is a second-order polynomial in the filter order and is a first-order polynomial in the filter wordlength. Unlike conventional methods where each coefficient is allocated a fixed number of SPT terms, our method allows the number of SPT terms for each coefficient to vary subject to the number of SPT terms for the entire filter. This provides us with the possibility of finding a better filter without increasing the number of adders, which determines the realization cost for a given filter length. Application of the algorithm to FIR filter designs shows that it achieves up to 8.9 dB improvement over simulated annealing and mixed integer linear programming on the normalized peak ripples of example filters.
Fri, 01 Jan 1993 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/816781993-01-01T00:00:00Z
- Self-timed precharge latchhttps://scholarbank.nus.edu.sg/handle/10635/81734Title: Self-timed precharge latch
Authors: Tan, Y.K.; Lim, Y.C.
Abstract: The use of a self-timed precharge latch (STPL) is proposed for the design of self-timed systems based on the four-cycle and two-cycle handshaking protocols. The techniques allow different data to be stored and computed in consecutive pipeline stages simultaneously without using a conventional data register. The techniques allow the propagation of data across the pipeline stage in a fast domino manner, parallel with the handshaking signals. The variable-length FIFOs designed using these techniques result in a significant reduction in silicon area and fall-through delay compared with those designed based on other techniques.
Mon, 01 Jan 1990 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/817341990-01-01T00:00:00Z
- Signed power-of-two (SPT) term allocation scheme for the design of digital filtershttps://scholarbank.nus.edu.sg/handle/10635/81739Title: Signed power-of-two (SPT) term allocation scheme for the design of digital filters
Authors: Lim, Yong-Ching; Yang, Rui; Li, Dongning; Song, Jianjian
Abstract: It is well known that if each coefficient value of a digital filter is a sum of SPT terms, the filter can be implemented without using multipliers. In the past decade, several methods had been developed for the design of filters whose coefficient values are sums of SPT terms. Most of these methods are for the design of filters where all the coefficient values have the same number of SPT terms. In this paper, we present a new method for allocating different number of SPT terms to each coefficient value keeping the total number of SPT terms fixed. Our technique yields excellent results.
Thu, 01 Jan 1998 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/817391998-01-01T00:00:00Z
- SIMPLE FAST ADAPTIVE ARRAY BASED ON A NULL STEERING BEAMFORMER.https://scholarbank.nus.edu.sg/handle/10635/81740Title: SIMPLE FAST ADAPTIVE ARRAY BASED ON A NULL STEERING BEAMFORMER.
Authors: Ko, C.C.; Lim, Y.C.; Ngan, K.N.
Abstract: The authors describe and analyze a simple adaptive array based on the use of perturbation algorithms on a null steering beamformer proposed by D. E. N. Davies (1967). The convergence time constants and misadjustments resulting from using these algorithms are derived. It is shown that by choosing the feedback factors appropriately the time constants can be roughly equalized, resulting in faster convergence behavior.
Wed, 01 Jan 1986 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/817401986-01-01T00:00:00Z
- Multiplierless realization of adaptive filters by nonuniform quantization of input signalhttps://scholarbank.nus.edu.sg/handle/10635/81559Title: Multiplierless realization of adaptive filters by nonuniform quantization of input signal
Authors: Li, Dongning; Ching Lim, Yong
Abstract: This paper presents a multiplierless realization structure for the implementation of adaptive digital filters. Multiplierless realization is achieved by quantizing input signals in such way that each input sample is expressed as a sum of a fixed number of signed power-of-two (SPT) terms. This simplifies all multiplications involving input signal data. Simulation results for suppressing a narrow-band interference in a direct-sequence spread-spectrum communication system show that the performance of our technique with input signal quantized to 2 SPT terms is comparable to a conventional filter with input uniformly quantized to 10 bits. However, our technique reduces the number of transistors required for realization in a custom VLSI circuit to about 1/3 of that required by conventional realization.
Sat, 01 Jan 1994 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/815591994-01-01T00:00:00Z
- Analysis and optimum design of the FFBhttps://scholarbank.nus.edu.sg/handle/10635/72481Title: Analysis and optimum design of the FFB
Authors: Lim, Yong Ching; Farhang-Boroujeny, B.
Abstract: A low complexity high selectivity fast filer bank (FFB) which does not involve down-sampling and up-sampling of signals has been developed in [8]. Since a single sampling rate is used throughout the filtering process, aliasing problem does not exist. In [8], the FFB was derived from the FFT. In this paper, we present an alternative derivation for the FFB. This alternative derivation renders detail analysis of the performance of the FFB possible. This in turn leads to the optimum design of the FFB. In this paper, we also show by means of an example that the computational complexity of the FFB is significantly less than that of a single-rate polyphase filter.
Sat, 01 Jan 1994 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/724811994-01-01T00:00:00Z
- New multiple-function logic familyhttps://scholarbank.nus.edu.sg/handle/10635/81593Title: New multiple-function logic family
Authors: Tan, Y.K.; Lim, Y.C.; Kwok, C.Y.; Ling, C.H.
Abstract: A novel technique is presented for the design of a multiple-function logic (MFL) circuit which generates several Boolean functions simultaneously and shares the transistors implementing the common subexpression of these Boolean functions. For certain circuits, this approach requires fewer transistors and reduces the gate delays compared with the conventional approach where the common subexpression is implemented as a new intermediate function, shared by other gates to generate the required outputs. The application of the technique to a CMOS domino logic 4-b carry-lookahead generator and an nMOS 1-of-8 decoder results in savings of 45.0% and 42.5%, respectively, in the number of transistors needed.
Sun, 01 Jan 1989 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/815931989-01-01T00:00:00Z
- Weighted least squares algorithm for the design of lattice-type perfect reconstruction cosine modulated filter bankshttps://scholarbank.nus.edu.sg/handle/10635/81358Title: Weighted least squares algorithm for the design of lattice-type perfect reconstruction cosine modulated filter banks
Authors: Goh, C.K.; Lim, Y.C.; Yang, R.
Abstract: This paper presents a weighted least squares (WLS) algorithm for the design of lattice-type perfect reconstruction (PR) cosine modulated filter banks. The design of such a filter bank is formulated as a WLS problem with respect to the lattice coefficients, incorporating the condition that a number of the zeros of the prototype filter must be at specific locations in the stopband. Our iterative algorithm needs only a few iterations to derive a set of lattice coefficients which optimizes this WLS problem, while providing flexible control of the prototype filter's stopband ripples. By specifying appropriate zeros of the prototype filter in the stopband, good designs with no DC leakage can be easily obtained.
Fri, 01 Jan 1999 00:00:00 GMThttps://scholarbank.nus.edu.sg/handle/10635/813581999-01-01T00:00:00Z