Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/99526
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dc.titleHardware-driven prefetching for pointer data references
dc.contributor.authorChi, Chi-Hung
dc.contributor.authorCheung, Chin-Ming
dc.date.accessioned2014-10-27T06:05:00Z
dc.date.available2014-10-27T06:05:00Z
dc.date.issued1998
dc.identifier.citationChi, Chi-Hung,Cheung, Chin-Ming (1998). Hardware-driven prefetching for pointer data references. Proceedings of the International Conference on Supercomputing : 377-384. ScholarBank@NUS Repository.
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/99526
dc.description.abstractEffectiveness of a data prefetch mechanism lies in the exploration of regular access patterns found in the memory reference address sequence. Previous research shows that selective prefetch schemes are effective for linearly accessed memory references, including instructions and data array accesses with constant strides. Extending them to pointer accesses limits their effectiveness because such linear function nor highly accurate probabilistic model is difficult to find. In this paper, a fresh look into data access regularity and predictability from the runtime self-modification of register values is proposed. Then, a hardware driven prefetch scheme, called the Reference Value Prediction Caching (RVPC), is proposed to realize this predictability model. This RVPC scheme is based on the detection of self-modifying instructions in loops and the use of self-modifying registers in data references. Simulation result shows that significant reduction in memory latency can be obtained, especially in non-pointer data structures including linked lists and trees.
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentINFORMATION SYSTEMS & COMPUTER SCIENCE
dc.description.sourcetitleProceedings of the International Conference on Supercomputing
dc.description.page377-384
dc.description.coden215
dc.identifier.isiutNOT_IN_WOS
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