Please use this identifier to cite or link to this item: https://doi.org/10.1109/43.503937
DC FieldValue
dc.titleMinimum fault coverage in memory arrays: A fast algorithm and probabilistic analysis
dc.contributor.authorLow, C.-P.
dc.contributor.authorLeong, H.W.
dc.date.accessioned2014-10-27T06:03:03Z
dc.date.available2014-10-27T06:03:03Z
dc.date.issued1996
dc.identifier.citationLow, C.-P., Leong, H.W. (1996). Minimum fault coverage in memory arrays: A fast algorithm and probabilistic analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 15 (6) : 681-690. ScholarBank@NUS Repository. https://doi.org/10.1109/43.503937
dc.identifier.issn02780070
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/99336
dc.description.abstractThe problem of reconfiguring memory arrays using spare rows and spare columns is known to be NP-complete and has received a great deal of attention in recent years. For reason of cost effectiveness, it is desirable in practice to flnd minimum reconfiguration solutions. While numerous algorithms have been proposed to find minimum reconfiguration solutions, they all run in worst case exponential time complexities. On the other hand, existing heuristic algorithms with fast polynomial running time cannot guarantee minimum solutions. This paper presents a provably good heuristic algorithm for finding minimum reconfiguration solution. Using random bipartite graphs, we prove that the reconfiguration problem is almost always optimally solvable with our new algorithm in polynomial time for all practical purposes. We also show that our algorithm can be used to estimate the number of spare rows and columns that are required to achieve a given percentage of yield for RRAM's with known defect probabilities. © 1996 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/43.503937
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentINFORMATION SYSTEMS & COMPUTER SCIENCE
dc.description.doi10.1109/43.503937
dc.description.sourcetitleIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
dc.description.volume15
dc.description.issue6
dc.description.page681-690
dc.description.codenITCSD
dc.identifier.isiutA1996UU14200011
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