Interface Engineering in the High-k Dielectric Gate Stacks

Please use this identifier to cite or link to this item: https://doi.org/10.1002/9783527646340.ch9

DC Field	Value
dc.title	Interface Engineering in the High-k Dielectric Gate Stacks
dc.contributor.author	Wang, S.
dc.contributor.author	Feng, Y.
dc.contributor.author	Huan, A.C.H.
dc.date.accessioned	2014-10-16T09:53:46Z
dc.date.available	2014-10-16T09:53:46Z
dc.date.issued	2012-08-23
dc.identifier.citation	Wang, S.,Feng, Y.,Huan, A.C.H. (2012-08-23). Interface Engineering in the High-k Dielectric Gate Stacks. High-k Gate Dielectrics for CMOS Technology : 293-318. ScholarBank@NUS Repository. <a href="https://doi.org/10.1002/9783527646340.ch9" target="_blank">https://doi.org/10.1002/9783527646340.ch9</a>
dc.identifier.isbn	9783527330324
dc.identifier.uri	http://scholarbank.nus.edu.sg/handle/10635/98980
dc.description.uri	http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1002/9783527646340.ch9
dc.source	Scopus
dc.subject	Gate dielectric
dc.subject	Heterojunction
dc.subject	High-k dielectric material
dc.subject	Keywords: band offset
dc.subject	Metal/semiconductor interfaces
dc.subject	Schottky barrier height
dc.type	Others
dc.contributor.department	PHYSICS
dc.description.doi	10.1002/9783527646340.ch9
dc.description.sourcetitle	High-k Gate Dielectrics for CMOS Technology
dc.description.page	293-318
dc.identifier.isiut	NOT_IN_WOS
Appears in Collections:	Staff Publications

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