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https://doi.org/10.1109/TED.2004.826866
Title: | Laser thermal processing of amorphous silicon gates to reduce poly-depletion in CMOS devices | Authors: | Chong, Y.F. Gossmann, H.-J.L. Pey, K.-L. Thompson, M.O. Wee, A.T.S. Tung, C.H. |
Keywords: | Boron penetration Gate oxide reliability Laser thermal processing (LTP) Poly-depletion |
Issue Date: | May-2004 | Citation: | Chong, Y.F., Gossmann, H.-J.L., Pey, K.-L., Thompson, M.O., Wee, A.T.S., Tung, C.H. (2004-05). Laser thermal processing of amorphous silicon gates to reduce poly-depletion in CMOS devices. IEEE Transactions on Electron Devices 51 (5) : 669-676. ScholarBank@NUS Repository. https://doi.org/10.1109/TED.2004.826866 | Abstract: | One major challenge in advanced CMOS technology is to have adequate dopant activation at the polycrystalline silicon (poly-Si) gate/gate oxide interface to minimize the poly-Si depletion effect. In this paper, laser thermal processing (LTP) was employed to fabricate single or dual-layer poly-Si-gated MOS capacitors with ultrathin gate oxides. Capacitance-voltage data show that the carrier concentration at the poly-Si gate/gate oxide interface increases substantially when the devices are subjected to LTP prior to a rapid thermal anneal (RTA). Thus, LTP readily reduces the poly-depletion thickness in MOS devices. For p+-gated capacitors, this is achieved with boron penetration that is equivalent to the control sample with 1000°C, 5 s RTA (without LTP). In addition, results from secondary ion mass spectrometry indicate that the concentration of dopants near the critical gate/gate oxide interface increases significantly after a post-LTP anneal, in good agreement with the electrical data. Time-dependent dielectric breakdown studies show that the gate oxide reliability is not degraded even after LTP at high fluences. | Source Title: | IEEE Transactions on Electron Devices | URI: | http://scholarbank.nus.edu.sg/handle/10635/97046 | ISSN: | 00189383 | DOI: | 10.1109/TED.2004.826866 |
Appears in Collections: | Staff Publications |
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