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Please use this identifier to cite or link to this item: https://doi.org/10.1016/j.mee.2007.04.050
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dc.titleBand engineering in the high-k dielectrics gate stacks
dc.contributor.authorWang, S.J.
dc.contributor.authorDong, Y.F.
dc.contributor.authorFeng, Y.P.
dc.contributor.authorHuan, A.C.H.
dc.date.accessioned2014-10-16T09:16:31Z
dc.date.available2014-10-16T09:16:31Z
dc.date.issued2007-09
dc.identifier.citationWang, S.J., Dong, Y.F., Feng, Y.P., Huan, A.C.H. (2007-09). Band engineering in the high-k dielectrics gate stacks. Microelectronic Engineering 84 (9-10) : 2332-2335. ScholarBank@NUS Repository. https://doi.org/10.1016/j.mee.2007.04.050
dc.identifier.issn01679317
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/95848
dc.description.abstractIn this report, the band alignment related issues for high-k gate stacks have been discussed and the band engineering has been studied by combinational characterization of in-situ x-ray photoemission spectroscopy (XPS), high resolution transmission electron microscopy (HRTEM) and first-principles calculations based on density functional theory (DFT). The results show that band alignments at metal-gate/high-κ interfaces can be engineered to satisfy the application for CMOS devices through the interface structure-control. © 2007 Elsevier B.V. All rights reserved.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1016/j.mee.2007.04.050
dc.sourceScopus
dc.subjectBand alignment
dc.subjectHigh-k gate stacks
dc.subjectInterface
dc.subjectMetal gate
dc.typeArticle
dc.contributor.departmentPHYSICS
dc.description.doi10.1016/j.mee.2007.04.050
dc.description.sourcetitleMicroelectronic Engineering
dc.description.volume84
dc.description.issue9-10
dc.description.page2332-2335
dc.description.codenMIENE
dc.identifier.isiut000247378600115
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