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|Title:||V t balancing and device sizing towards high yield of sub-threshold static logic gates||Authors:||Pu, Y.
De Gyvez, J.P.
|Issue Date:||2007||Citation:||Pu, Y.,De Gyvez, J.P.,Corporaal, H.,Ha, Y. (2007). V t balancing and device sizing towards high yield of sub-threshold static logic gates. Proceedings of the International Symposium on Low Power Electronics and Design : 355-358. ScholarBank@NUS Repository. https://doi.org/10.1145/1283780.1283857||Abstract:||Operating digital circuits in the sub-threshold region is potentially a solution for ultra low-power applications. However, simply reducing supply voltage well below threshold voltage causes functional yield degradation. In this paper, we show that imbalanced V T of pMOS and nMOS transistors and V T mismatch of paired transistors are especially detrimental to sub-threshold functional yield. We propose a variability-driven digital gate design approach which includes balancing process-corner V T shifts of nMOS/pMOS transistors with a low-overhead bulk-bias circuitry and a gate-sizing approach that yields close to minimum size transistor dimensions. Results of Monte-Carlo simulations of a ring oscillator with 31 stages show that our solution can help to achieve a mean frequency speedup of 51.91% and energy/cycle saving of 19.67% on average. Copyright 2007 ACM.||Source Title:||Proceedings of the International Symposium on Low Power Electronics and Design||URI:||http://scholarbank.nus.edu.sg/handle/10635/84346||ISBN:||1595937099||ISSN:||15334678||DOI:||10.1145/1283780.1283857|
|Appears in Collections:||Staff Publications|
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