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https://doi.org/10.1109/IEDM.2007.4418868
Title: | Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory | Authors: | Fu, J. Buddharaju, K.D. Teo, S.H.G. Zhu, C. Yu, M.B. Singh, N. Lo, G.Q. Balasubramanian, N. Kwong, D.L. |
Issue Date: | 2007 | Citation: | Fu, J., Buddharaju, K.D., Teo, S.H.G., Zhu, C., Yu, M.B., Singh, N., Lo, G.Q., Balasubramanian, N., Kwong, D.L. (2007). Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory. Technical Digest - International Electron Devices Meeting, IEDM : 79-82. ScholarBank@NUS Repository. https://doi.org/10.1109/IEDM.2007.4418868 | Abstract: | Trap layer engineered gate-all-around (GAA) silicon nanowire SONOS memory showing excellent device performance is demonstrated for the first time. Nitride and silicon nanocrystal (Si-NC) has have been incorporated as the engineered charge trapping layer. Fast transient memory characteristic is shown owing to the nanowire channel structure. The device with embedded Si-NC achieves even faster higher memory speed and increased window, up to 3.2 V ΔV th shift for 1 μs and 6.25 V memory window. The nanowire based non-volatile SONOS memory is promising for the future high speed and low power NAND-type flash memory application. © 2007 IEEE. | Source Title: | Technical Digest - International Electron Devices Meeting, IEDM | URI: | http://scholarbank.nus.edu.sg/handle/10635/84323 | ISSN: | 01631918 | DOI: | 10.1109/IEDM.2007.4418868 |
Appears in Collections: | Staff Publications |
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