Planar and multiple-gate transistors with silicon-carbon source/drain

Abstract

We explore technology options for the enhancement of electron mobility in n-FETs, focusing on channel strain engineering using lattice-mismatched source/drain (S/D) materials. By employing silicon-carbon (Si 1-yCy) in the S/D regions, lateral tensile strain in the Si channel is induced for electron mobility and drive current IDsat improvement. Further performance enhancement is achieved by the combination of multiple-stressors, e.g. Si1-yCy S/D and silicon nitride SiN liner stressor. This is demonstrated on bulk planar transistors, silicon-on-insulator planar transistors, and multiple-gate transistors. Process integration issues and strain enhancement approaches are discussed. © 2006 IEEE.