Please use this identifier to cite or link to this item: https://doi.org/10.1109/VTSA.2009.5159297
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dc.titleP-FinFETs with Al segregated NiSi/p+-Si source/drain contact junction for series resistance reduction
dc.contributor.authorSinha, M.
dc.contributor.authorLee, R.T.P.
dc.contributor.authorDevi, S.N.
dc.contributor.authorLo, G.-Q.
dc.contributor.authorChor, E.F.
dc.contributor.authorYeo, Y.-C.
dc.date.accessioned2014-10-07T04:48:35Z
dc.date.available2014-10-07T04:48:35Z
dc.date.issued2009
dc.identifier.citationSinha, M., Lee, R.T.P., Devi, S.N., Lo, G.-Q., Chor, E.F., Yeo, Y.-C. (2009). P-FinFETs with Al segregated NiSi/p+-Si source/drain contact junction for series resistance reduction. International Symposium on VLSI Technology, Systems, and Applications, Proceedings : 74-75. ScholarBank@NUS Repository. https://doi.org/10.1109/VTSA.2009.5159297
dc.identifier.isbn9781424427857
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/84082
dc.description.abstractThis paper demonstrates the integration of Al segregated NiSi/p +-Si S/D contact junction in p-FinFETs for parasitic series resistance reduction. Al is introduced by ion implant into p+ S/D region followed by nickel deposition and silicidation. Drive current enhancement of ∼15 % is achieved without any degradation of short channel effects. This is attributed to the lowering of Φp B of NiSi on p-Si from 0.4 eV to 0.12 eV with low Al dose of 2 × 1014 atoms-cm-2, leading to lowering of contact resistance at NiSi/p +-Si S/D junction. ©2009 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/VTSA.2009.5159297
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/VTSA.2009.5159297
dc.description.sourcetitleInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
dc.description.page74-75
dc.identifier.isiut000272451000032
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