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|Title:||Nanowire FETs for Low Power CMOS Applications Featuring Novel Gate-All-Around Single Metal FUSI Gates with Dual φ m and v T Tune-ability||Authors:||Jiang, Y.
|Issue Date:||2008||Citation:||Jiang, Y.,Liow, T.Y.,Singh, N.,Tan, L.H.,Lo, G.Q.,Chan, D.S.H.,Kwong, D.L. (2008). Nanowire FETs for Low Power CMOS Applications Featuring Novel Gate-All-Around Single Metal FUSI Gates with Dual φ m and v T Tune-ability. Technical Digest - International Electron Devices Meeting, IEDM : -. ScholarBank@NUS Repository. https://doi.org/10.1109/IEDM.2008.4796836||Abstract:||A simple and cost-effective single metal gate scheme was successfully demonstrated to form gate-all-around (GAA) nanowire FETs with optimized dual V T for low power CMOS applications. FUSI gate-induced stress effects were shown to be of great relevance to device performance. At an I off of 20 pA/μm, superior I on of 1180 and 405 μA/μm were obtained for NFETs and PFETs at a V DD of 1.2 V.||Source Title:||Technical Digest - International Electron Devices Meeting, IEDM||URI:||http://scholarbank.nus.edu.sg/handle/10635/84000||ISBN:||9781424423781||ISSN:||01631918||DOI:||10.1109/IEDM.2008.4796836|
|Appears in Collections:||Staff Publications|
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