Interface barrier abruptness and work function requirements for scaling Schottky source-drain MOS transistors

Abstract

Schottky source-drain (S/D) MOS transistor coupled with metal gate is a promising alternative to the conventional poly-Si gate and doped S/D MOSFET technology [1-2]. This paper explores through simulations the effect of metal S/D WF and the gradual change of barrier profile at the metal-semiconductor interface and in the few nanometers space around it on the n/p channel device performance. We present the S/D workfunction (WF) requirements for ultra short channel device design for the first time. Through modeling and fabrication, we also present the underlying physical explanation behind the existence of dual slope in Id-Vg characteristics of metal S/D and Gate MOSFETs. © 2006 IEEE.