Please use this identifier to cite or link to this item:
https://doi.org/10.1109/VTSA.2008.4530782
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dc.title | In-situ surface passivation and metal-gate/high-k dielectric stack formation for N-channel gallium arsenide metal-oxide-semiconductor field-effect transistors | |
dc.contributor.author | Chin, H.-C. | |
dc.contributor.author | Zhu, M. | |
dc.contributor.author | Whang, S.-J. | |
dc.contributor.author | Tung, C.-H. | |
dc.contributor.author | Samudra, G.S. | |
dc.contributor.author | Yeo, Y.-C. | |
dc.date.accessioned | 2014-10-07T04:45:52Z | |
dc.date.available | 2014-10-07T04:45:52Z | |
dc.date.issued | 2008 | |
dc.identifier.citation | Chin, H.-C., Zhu, M., Whang, S.-J., Tung, C.-H., Samudra, G.S., Yeo, Y.-C. (2008). In-situ surface passivation and metal-gate/high-k dielectric stack formation for N-channel gallium arsenide metal-oxide-semiconductor field-effect transistors. International Symposium on VLSI Technology, Systems, and Applications, Proceedings : 26-27. ScholarBank@NUS Repository. https://doi.org/10.1109/VTSA.2008.4530782 | |
dc.identifier.isbn | 9781424416158 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/83846 | |
dc.description.abstract | We demonstrate an in-situ surface passivation technique for the formation of high-permittivity gate dielectric on GaAs using a multiple chamber metal-organic chemical vapor deposition (MOCVD) system. In-situ vacuum annealing and SiH4 treatment were performed prior to high-k dielectric deposition. This novel passivation scheme effectively suppresses the formation of Ga or As oxide during the high-k dielectric deposition process. Self-aligned GaAs MOSFETs were fabricated, showing excellent device characteristics with a peak electron mobility of 1244.4 cm2/Vs. The effect of post deposition anneal (PDA) temperature and forming gas anneal (FGA) conditions on the GaAs MOS capacitors was also investigated. Using HfAlO as gate dielectric, the in-situ surface passivated GaAs MOS capacitors demonstrate low frequency dispersion, small hysteresis and low midgap interface state density (D it) of 2.4 × 1011 to 7.5 × 1011 cm-2.eV-1, determined by high frequency conductance method. © 2008 IEEE. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/VTSA.2008.4530782 | |
dc.source | Scopus | |
dc.type | Conference Paper | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.description.doi | 10.1109/VTSA.2008.4530782 | |
dc.description.sourcetitle | International Symposium on VLSI Technology, Systems, and Applications, Proceedings | |
dc.description.page | 26-27 | |
dc.identifier.isiut | 000256564900011 | |
Appears in Collections: | Staff Publications |
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