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|Title:||In-situ surface passivation and metal-gate/high-k dielectric stack formation for N-channel gallium arsenide metal-oxide-semiconductor field-effect transistors||Authors:||Chin, H.-C.
|Issue Date:||2008||Citation:||Chin, H.-C., Zhu, M., Whang, S.-J., Tung, C.-H., Samudra, G.S., Yeo, Y.-C. (2008). In-situ surface passivation and metal-gate/high-k dielectric stack formation for N-channel gallium arsenide metal-oxide-semiconductor field-effect transistors. International Symposium on VLSI Technology, Systems, and Applications, Proceedings : 26-27. ScholarBank@NUS Repository. https://doi.org/10.1109/VTSA.2008.4530782||Abstract:||We demonstrate an in-situ surface passivation technique for the formation of high-permittivity gate dielectric on GaAs using a multiple chamber metal-organic chemical vapor deposition (MOCVD) system. In-situ vacuum annealing and SiH4 treatment were performed prior to high-k dielectric deposition. This novel passivation scheme effectively suppresses the formation of Ga or As oxide during the high-k dielectric deposition process. Self-aligned GaAs MOSFETs were fabricated, showing excellent device characteristics with a peak electron mobility of 1244.4 cm2/Vs. The effect of post deposition anneal (PDA) temperature and forming gas anneal (FGA) conditions on the GaAs MOS capacitors was also investigated. Using HfAlO as gate dielectric, the in-situ surface passivated GaAs MOS capacitors demonstrate low frequency dispersion, small hysteresis and low midgap interface state density (D it) of 2.4 × 1011 to 7.5 × 1011 cm-2.eV-1, determined by high frequency conductance method. © 2008 IEEE.||Source Title:||International Symposium on VLSI Technology, Systems, and Applications, Proceedings||URI:||http://scholarbank.nus.edu.sg/handle/10635/83846||ISBN:||9781424416158||DOI:||10.1109/VTSA.2008.4530782|
|Appears in Collections:||Staff Publications|
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