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|Title:||Enhanced Ge MOS device performance through a novel post-gate CF 4-plasma treatment process||Authors:||Xie, R.
|Issue Date:||2008||Citation:||Xie, R., Thamarai, M., Sun, Z., Yu, M., Lai, D.M.Y., Chan, L., Zhu, C. (2008). Enhanced Ge MOS device performance through a novel post-gate CF 4-plasma treatment process. ECS Transactions 16 (10) : 707-716. ScholarBank@NUS Repository. https://doi.org/10.1149/1.2986827||Abstract:||A post-gate CF4-plasma treatment process is proposed and demonstrated on Ge MOS devices and the effects of F incorporation have been extensively studied on both high-k/Ge gate stacks without any surface passivation and with Si surface passivation. Our results show that: (1) F is effectively introduced into the gate stack by CF4 treatment and segregates near high-k/Ge interface; (2) Electrical characteristics like D it, gate leakage, C-V hysteresis and breakdown voltage are improved after F incorporation; (3) Post-gate CF4 treatment is also compatible with pre-gate surface passivation, and it can further enhance the device performance. By combining Si surface passivation and post-gate CF4 treatment, interface quality has been greatly improved for high-k/Ge gate stack and a high peak hole mobility of 376 cm4/Vs has been achieved for Ge pMOSFETs. ©The Electrochemical Society.||Source Title:||ECS Transactions||URI:||http://scholarbank.nus.edu.sg/handle/10635/83699||ISBN:||9781566776561||ISSN:||19385862||DOI:||10.1149/1.2986827|
|Appears in Collections:||Staff Publications|
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