Please use this identifier to cite or link to this item: https://doi.org/10.1016/S0167-9317(03)00050-9
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dc.titleEffects of rapid thermal annealing time and ambient temperature on the charge storage capability of SiO2/pure Ge/rapid thermal oxide memory structure
dc.contributor.authorHeng, C.L.
dc.contributor.authorTeo, L.W.
dc.contributor.authorHo, V.
dc.contributor.authorTay, M.S.
dc.contributor.authorLei, Y.
dc.contributor.authorChoi, W.K.
dc.contributor.authorChim, W.K.
dc.date.accessioned2014-10-07T04:44:00Z
dc.date.available2014-10-07T04:44:00Z
dc.date.issued2003-04
dc.identifier.citationHeng, C.L., Teo, L.W., Ho, V., Tay, M.S., Lei, Y., Choi, W.K., Chim, W.K. (2003-04). Effects of rapid thermal annealing time and ambient temperature on the charge storage capability of SiO2/pure Ge/rapid thermal oxide memory structure. Microelectronic Engineering 66 (1-4) : 218-223. ScholarBank@NUS Repository. https://doi.org/10.1016/S0167-9317(03)00050-9
dc.identifier.issn01679317
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/83684
dc.description.abstractA metal-insulator-semiconductor device with a tri-layer structure consisting of sputtered silicon dioxide (SiO2) (∼ 50 nm)-evaporated pure germanium (Ge) (2.3 nm)-rapid thermal oxidation (RTO) oxide (5 nm) was fabricated on a p-type silicon (Si) substrate. This structure was rapid thermal annealed at 1000 °C in argon. For the as-prepared structure and those that were annealed from 10 to 400 s, it was observed that the hysteresis of the capacitance versus voltage (C-V) curves increased from ∼ 1.5 to 10 V. This indicated that the charge storage capability of the structure improved with increasing annealing time. From our transmission electron microscope results, we observed that as the annealing time increased, more Ge nanocrystals were formed. When the ambient temperature was increased from 25 to 150 °C, the width of the hysteresis of our devices reduced. The charge storage mechanism of the Ge nanocrystals was explained in terms of charging/discharging from traps at the internal/surface of Ge nanocrystals and tunneling of charges to the interface states at the Si-RTO oxide interface. © Elsevier Science B.V. All rights reserved.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1016/S0167-9317(03)00050-9
dc.sourceScopus
dc.subjectCharge storage
dc.subjectGe nanocrystals
dc.subjectRapid thermal annealing
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1016/S0167-9317(03)00050-9
dc.description.sourcetitleMicroelectronic Engineering
dc.description.volume66
dc.description.issue1-4
dc.description.page218-223
dc.description.codenMIENE
dc.identifier.isiut000182725500035
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