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https://doi.org/10.1109/ICSICT.2006.306123
Title: | Effective suppression of fermi level pinning in poly-Si/HfO2 gate stack by using poly-SiGe gate | Authors: | Yu, X. Yu, M. Zhu, C. |
Issue Date: | 2007 | Citation: | Yu, X.,Yu, M.,Zhu, C. (2007). Effective suppression of fermi level pinning in poly-Si/HfO2 gate stack by using poly-SiGe gate. ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings : 149-151. ScholarBank@NUS Repository. https://doi.org/10.1109/ICSICT.2006.306123 | Abstract: | In this work, we have demonstrated that the Fermi level pinning in poly-Si/HfO2 can be effectively suppressed by using poly-SiGe gate. Threshold voltage of -1.02 V in poly-Si/HfO2 PFET was tuned to -0.81 V in poly-Si/Al2O3/HfO2, and further reduced to -0.49 V in poly-Si/poly-SiGe/Al2O3/HfO2. At the same time, Vth, of 0.3 V for NFET was achieved in this poly-SiGe gate stack. Moreover, Vuth stability was remarkably improved by using poly-SiGe gate and Al2O3 capping layer. The improvements shown in this poly-SiGe gate stack could be due to the suppressed formation of oxygen vacancies. © 2006 IEEE. | Source Title: | ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings | URI: | http://scholarbank.nus.edu.sg/handle/10635/83675 | ISBN: | 1424401615 | DOI: | 10.1109/ICSICT.2006.306123 |
Appears in Collections: | Staff Publications |
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