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Title: Demonstration of a new approach towards 0.25V Low-Vt CMOS using Ni-based FUSI
Authors: Yu, H.Y.
Kittl, J.A.
Lauwers, A.
Singanamalla, R.
Demeurisse, C.
Kubicek, S.
Augendre, E.
Veloso, A.
Brus, S.
Vrancken, C.
Hoffmann, T.
Mertens, S.
Onsia, B.
Verbeeck, R.
Demand, M.
Rothchild, A.
Froment, B.
Van Dal, M.
De Meyer, K.
Li, M.F. 
Chen, J.D. 
Jurczak, M.
Absil, P.P.
Biesemans, S.
Issue Date: 2006
Citation: Yu, H.Y.,Kittl, J.A.,Lauwers, A.,Singanamalla, R.,Demeurisse, C.,Kubicek, S.,Augendre, E.,Veloso, A.,Brus, S.,Vrancken, C.,Hoffmann, T.,Mertens, S.,Onsia, B.,Verbeeck, R.,Demand, M.,Rothchild, A.,Froment, B.,Van Dal, M.,De Meyer, K.,Li, M.F.,Chen, J.D.,Jurczak, M.,Absil, P.P.,Biesemans, S. (2006). Demonstration of a new approach towards 0.25V Low-Vt CMOS using Ni-based FUSI. Digest of Technical Papers - Symposium on VLSI Technology : 98-99. ScholarBank@NUS Repository.
Abstract: This report discusses a new and practical approach to implement low V t bulk CMOS using Ni-based FUSI MOSFETs. On the nFET, we demonstrate for the first time that incorporating Yb by ion implantation can achieve similar reduction of effective work function (WF) compared to alloying making it a candidate for CMOS integration. We complement our previous work on WF modulation by Yb on NiSi/SiON with new data on NiSi/HfSiON and NiGeSi/HfSiON. On the pFET, we study the effect of Al and Pt on Ni-rich FUSI and integrate it with a SiGe-channel. Integration into our reference devices resulted in a V1 reduction from 0.55/0.61V down to 0.30/0.25V for nFET (NiSi:Yb gate) and pFET (Ni 2Si:Pt gate + SiGe channel) respectively on SiON without degradation of the dielectric integrity and long channel mobility, and without an increase in gate leakage and Dit. © 2006 IEEE.
Source Title: Digest of Technical Papers - Symposium on VLSI Technology
ISBN: 1424400058
ISSN: 07431562
Appears in Collections:Staff Publications

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