Please use this identifier to cite or link to this item:
https://doi.org/10.1149/1.2986751
DC Field | Value | |
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dc.title | Carbon- and tin- Incorporated source/drain stressors for CMOS transistors | |
dc.contributor.author | Yeo, Y.-C. | |
dc.date.accessioned | 2014-10-07T04:42:13Z | |
dc.date.available | 2014-10-07T04:42:13Z | |
dc.date.issued | 2008 | |
dc.identifier.citation | Yeo, Y.-C. (2008). Carbon- and tin- Incorporated source/drain stressors for CMOS transistors. ECS Transactions 16 (10) : 39-46. ScholarBank@NUS Repository. https://doi.org/10.1149/1.2986751 | |
dc.identifier.isbn | 9781566776561 | |
dc.identifier.issn | 19385862 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/83527 | |
dc.description.abstract | We explore several technology options for forming latticemismatched source/drain (S/D) stressors for enhancing the performance of complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Recent research on silicon-carbon (Si:C or Sil-yCy) S/D stressors for n-FETs will be reviewed. Device integration work involving epitaxial Si:C S/D with high carbon concentration and in situ doping, as well as alternative technologies for forming Si:C S/D, e.g. using implantation and anneal, will be discussed. For p-FETs, tin-incorporated S/D stressors will be explored. Integration of new stressors in advanced device architectures is expected to enable the realization of ultimate CMOS performance. ©The Electrochemical Society. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1149/1.2986751 | |
dc.source | Scopus | |
dc.type | Conference Paper | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.description.doi | 10.1149/1.2986751 | |
dc.description.sourcetitle | ECS Transactions | |
dc.description.volume | 16 | |
dc.description.issue | 10 | |
dc.description.page | 39-46 | |
dc.identifier.isiut | 000273336700004 | |
Appears in Collections: | Staff Publications |
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