Carbon- and tin- Incorporated source/drain stressors for CMOS transistors

Abstract

We explore several technology options for forming latticemismatched source/drain (S/D) stressors for enhancing the performance of complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Recent research on silicon-carbon (Si:C or Sil-yCy) S/D stressors for n-FETs will be reviewed. Device integration work involving epitaxial Si:C S/D with high carbon concentration and in situ doping, as well as alternative technologies for forming Si:C S/D, e.g. using implantation and anneal, will be discussed. For p-FETs, tin-incorporated S/D stressors will be explored. Integration of new stressors in advanced device architectures is expected to enable the realization of ultimate CMOS performance. ©The Electrochemical Society.