Please use this identifier to cite or link to this item: https://doi.org/10.1149/1.2986751
Title: Carbon- and tin- Incorporated source/drain stressors for CMOS transistors
Authors: Yeo, Y.-C. 
Issue Date: 2008
Citation: Yeo, Y.-C. (2008). Carbon- and tin- Incorporated source/drain stressors for CMOS transistors. ECS Transactions 16 (10) : 39-46. ScholarBank@NUS Repository. https://doi.org/10.1149/1.2986751
Abstract: We explore several technology options for forming latticemismatched source/drain (S/D) stressors for enhancing the performance of complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Recent research on silicon-carbon (Si:C or Sil-yCy) S/D stressors for n-FETs will be reviewed. Device integration work involving epitaxial Si:C S/D with high carbon concentration and in situ doping, as well as alternative technologies for forming Si:C S/D, e.g. using implantation and anneal, will be discussed. For p-FETs, tin-incorporated S/D stressors will be explored. Integration of new stressors in advanced device architectures is expected to enable the realization of ultimate CMOS performance. ©The Electrochemical Society.
Source Title: ECS Transactions
URI: http://scholarbank.nus.edu.sg/handle/10635/83527
ISBN: 9781566776561
ISSN: 19385862
DOI: 10.1149/1.2986751
Appears in Collections:Staff Publications

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